blob: 5bb3b38a13380848417aa14afbbd41c27b0c4371 [file] [log] [blame]
Stefan Reinauer00636b02012-04-04 00:08:51 +02001/*
2 * coreboot UEFI PEI wrapper
3 *
4 * Copyright (c) 2011, Google Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * * Neither the name of Google Inc. nor the
15 * names of its contributors may be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT,
22 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
25 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#ifndef PEI_DATA_H
31#define PEI_DATA_H
32
Vadim Bendebury48a4a7f2012-06-07 18:47:13 -070033typedef void (*tx_byte_func)(unsigned char byte);
34#define PEI_VERSION 2
Stefan Reinauer00636b02012-04-04 00:08:51 +020035struct pei_data
36{
37 uint32_t pei_version;
38 uint32_t mchbar;
39 uint32_t dmibar;
40 uint32_t epbar;
41 uint32_t pciexbar;
42 uint16_t smbusbar;
43 uint32_t wdbbar;
44 uint32_t wdbsize;
45 uint32_t hpet_address;
46 uint32_t rcba;
47 uint32_t pmbase;
48 uint32_t gpiobase;
49 uint32_t thermalbase;
50 uint32_t system_type; // 0 Mobile, 1 Desktop/Server
51 uint32_t tseg_size;
52 uint8_t spd_addresses[4];
53 uint8_t ts_addresses[4];
54 int boot_mode;
55 int ec_present;
56 // 0 = leave channel enabled
57 // 1 = disable dimm 0 on channel
58 // 2 = disable dimm 1 on channel
59 // 3 = disable dimm 0+1 on channel
60 int dimm_channel0_disabled;
61 int dimm_channel1_disabled;
62 /* Seed values saved in CMOS */
63 uint32_t scrambler_seed;
64 uint32_t scrambler_seed_s3;
65 /* Data read from flash and passed into MRC */
66 unsigned char *mrc_input;
67 unsigned int mrc_input_len;
68 /* Data from MRC that should be saved to flash */
69 unsigned char *mrc_output;
70 unsigned int mrc_output_len;
71 /*
72 * Max frequency DDR3 could be ran at. Could be one of four values:
73 * 800, 1067, 1333, 1600
74 */
75 uint32_t max_ddr3_freq;
76 /*
77 * USB Port Configuration:
78 * [0] = enable
79 * [1] = overcurrent pin
80 * [2] = length
81 *
82 * Port Length
83 * MOBILE:
84 * < 0x050 = Setting 1 (back panel, 1-5in, lowest tx amplitude)
85 * < 0x140 = Setting 2 (back panel, 5-14in, highest tx amplitude)
86 * DESKTOP:
87 * < 0x080 = Setting 1 (front/back panel, <8in, lowest tx amplitude)
88 * < 0x130 = Setting 2 (back panel, 8-13in, higher tx amplitude)
89 * < 0x150 = Setting 3 (back panel, 13-15in, higest tx amplitude)
90 */
91 uint16_t usb_port_config[16][3];
92 /* SPD data array for onboard RAM. Specify address 0xf0,
93 * 0xf1, 0xf2, 0xf3 to index one of the 4 slots in
94 * spd_address for a given "DIMM".
95 */
96 uint8_t spd_data[4][256];
Vadim Bendebury48a4a7f2012-06-07 18:47:13 -070097 tx_byte_func tx_byte;
Stefan Reinauer00636b02012-04-04 00:08:51 +020098} __attribute__((packed));
99
100#endif