Add Intel Panther Point USB3 initialization
Add PEI updates and ACPI updates for supporting EHCI to XHCI
USB port support.
Change-Id: I9ace68a1b3950771aefb96c1319b8899291edd9a
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/2519
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h
index 8c907c1..fb56873 100644
--- a/src/northbridge/intel/sandybridge/pei_data.h
+++ b/src/northbridge/intel/sandybridge/pei_data.h
@@ -30,8 +30,16 @@
#ifndef PEI_DATA_H
#define PEI_DATA_H
+typedef struct {
+ uint16_t mode; // 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto
+ uint16_t hs_port_switch_mask; // 4 bit mask, 1: switchable, 0: not switchable
+ uint16_t preboot_support; // 0: No xHCI preOS driver, 1: xHCI preOS driver
+ uint16_t xhci_streams; // 0: Disable, 1: Enable
+} pch_usb3_controller_settings;
+
typedef void (*tx_byte_func)(unsigned char byte);
-#define PEI_VERSION 4
+#define PEI_VERSION 5
+
struct pei_data
{
uint32_t pei_version;
@@ -92,6 +100,8 @@
* < 0x150 = Setting 3 (back panel, 13-15in, higest tx amplitude)
*/
uint16_t usb_port_config[16][3];
+ /* See the usb3 struct above for details */
+ pch_usb3_controller_settings usb3;
/* SPD data array for onboard RAM. Specify address 0xf0,
* 0xf1, 0xf2, 0xf3 to index one of the 4 slots in
* spd_address for a given "DIMM".