blob: cda08b2d3f964578250e8157f7507c224f8c1e6e [file] [log] [blame]
Stefan Reinauer00636b02012-04-04 00:08:51 +02001/*
2 * coreboot UEFI PEI wrapper
3 *
4 * Copyright (c) 2011, Google Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * * Neither the name of Google Inc. nor the
15 * names of its contributors may be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT,
22 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
25 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#ifndef PEI_DATA_H
31#define PEI_DATA_H
32
33#define PEI_VERSION 1
34struct pei_data
35{
36 uint32_t pei_version;
37 uint32_t mchbar;
38 uint32_t dmibar;
39 uint32_t epbar;
40 uint32_t pciexbar;
41 uint16_t smbusbar;
42 uint32_t wdbbar;
43 uint32_t wdbsize;
44 uint32_t hpet_address;
45 uint32_t rcba;
46 uint32_t pmbase;
47 uint32_t gpiobase;
48 uint32_t thermalbase;
49 uint32_t system_type; // 0 Mobile, 1 Desktop/Server
50 uint32_t tseg_size;
51 uint8_t spd_addresses[4];
52 uint8_t ts_addresses[4];
53 int boot_mode;
54 int ec_present;
55 // 0 = leave channel enabled
56 // 1 = disable dimm 0 on channel
57 // 2 = disable dimm 1 on channel
58 // 3 = disable dimm 0+1 on channel
59 int dimm_channel0_disabled;
60 int dimm_channel1_disabled;
61 /* Seed values saved in CMOS */
62 uint32_t scrambler_seed;
63 uint32_t scrambler_seed_s3;
64 /* Data read from flash and passed into MRC */
65 unsigned char *mrc_input;
66 unsigned int mrc_input_len;
67 /* Data from MRC that should be saved to flash */
68 unsigned char *mrc_output;
69 unsigned int mrc_output_len;
70 /*
71 * Max frequency DDR3 could be ran at. Could be one of four values:
72 * 800, 1067, 1333, 1600
73 */
74 uint32_t max_ddr3_freq;
75 /*
76 * USB Port Configuration:
77 * [0] = enable
78 * [1] = overcurrent pin
79 * [2] = length
80 *
81 * Port Length
82 * MOBILE:
83 * < 0x050 = Setting 1 (back panel, 1-5in, lowest tx amplitude)
84 * < 0x140 = Setting 2 (back panel, 5-14in, highest tx amplitude)
85 * DESKTOP:
86 * < 0x080 = Setting 1 (front/back panel, <8in, lowest tx amplitude)
87 * < 0x130 = Setting 2 (back panel, 8-13in, higher tx amplitude)
88 * < 0x150 = Setting 3 (back panel, 13-15in, higest tx amplitude)
89 */
90 uint16_t usb_port_config[16][3];
91 /* SPD data array for onboard RAM. Specify address 0xf0,
92 * 0xf1, 0xf2, 0xf3 to index one of the 4 slots in
93 * spd_address for a given "DIMM".
94 */
95 uint8_t spd_data[4][256];
96} __attribute__((packed));
97
98#endif