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review.coreboot.org / coreboot / 60ec3656eb1d857caddba81852e3b99551fb1243 / . / src / mainboard / intel / d945gclf / mptable.c
blob: 13ebea4e0c1cc15891652a27ecf9283b1040aad5 [file] [log] [blame]
Angel Pons60ec3652020-04-03 01:22:13 +0200[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0-only */
2/* This file is part of the coreboot project. */
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]3
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]4#include <device/device.h>
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]5#include <arch/smp/mpspec.h>
Uwe Hermann74d1a6e2010-10-12 17:34:08 +0000[diff] [blame]6#include <arch/ioapic.h>
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]7#include <stdint.h>
8
Stefan Reinauer53b0ea42010-03-22 11:50:52 +0000[diff] [blame]9static void *smp_write_config_table(void *v)
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]10{
Elyes HAOUAS8da96e52016-09-22 21:20:54 +0200[diff] [blame]11 struct mp_config_table *mc;
Patrick Georgi5244e1b2010-11-21 14:41:07 +0000[diff] [blame]12 int isa_bus;
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]13
Elyes HAOUAS8da96e52016-09-22 21:20:54 +0200[diff] [blame]14 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]15
Patrick Georgic8feedd2012-02-16 18:43:25 +0100[diff] [blame]16 mptable_init(mc, LOCAL_APIC_ADDR);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]17
Elyes HAOUAS8da96e52016-09-22 21:20:54 +0200[diff] [blame]18 smp_write_processors(mc);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]19
Patrick Georgi5244e1b2010-11-21 14:41:07 +0000[diff] [blame]20 mptable_write_buses(mc, NULL, &isa_bus);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]21
22 /* I/O APICs: APIC ID Version State Address */
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800[diff] [blame]23 smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]24
25 /* Legacy Interrupts */
26
Patrick Georgic5b87c82010-05-20 15:28:19 +0000[diff] [blame]27 mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]28
29 /* Builtin devices on Bus 0 */
30 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10);
31 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13);
32 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17);
33 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13);
34 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12);
35 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10);
36 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x10);
37 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x10);
38 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x11);
39
40 /* Firewire 4:0.0 */
41 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10);
42
43 /* Old riser card */
44 // riser slot top 5:8.0
45 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14);
46 // riser slot middle 5:9.0
47 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, 0x15);
48 // riser slot bottom 5:a.0
49 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16);
50
51 /* New Riser Card */
52 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x30, 0x2, 0x14);
53 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x34, 0x2, 0x15);
54 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x38, 0x2, 0x16);
55
56 /* Onboard Ethernet */
57 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
58
59 /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
Patrick Georgi6eb7a532011-10-07 21:42:52 +0200[diff] [blame]60 mptable_lintsrc(mc, isa_bus);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]61
62 /* Compute the checksums */
Patrick Georgib0a9c5c2011-10-07 23:01:55 +0200[diff] [blame]63 return mptable_finalize(mc);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]64}
65
66unsigned long write_smp_table(unsigned long addr)
67{
68 void *v;
Patrick Georgic75c79b2011-10-07 22:41:07 +0200[diff] [blame]69 v = smp_write_floating_table(addr, 0);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]70 return (unsigned long)smp_write_config_table(v);
71}