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review.coreboot.org / coreboot / 93bcf24795a31b6b54095de3d0cc33417f68018d / . / src / mainboard / intel / d945gclf / mptable.c
blob: 62d014733f37f1a04ddbbb5980e7b78c8187d540 [file] [log] [blame]
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
Uwe Hermann2d2f0c12009-10-28 17:36:11 +0000[diff] [blame]7 * published by the Free Software Foundation; version 2 of the License.
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]13 */
14
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]15#include <device/device.h>
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]16#include <arch/smp/mpspec.h>
Uwe Hermann74d1a6e2010-10-12 17:34:08 +0000[diff] [blame]17#include <arch/ioapic.h>
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]18#include <stdint.h>
19
Stefan Reinauer53b0ea42010-03-22 11:50:52 +0000[diff] [blame]20static void *smp_write_config_table(void *v)
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]21{
Elyes HAOUAS8da96e52016-09-22 21:20:54 +0200[diff] [blame]22 struct mp_config_table *mc;
Patrick Georgi5244e1b2010-11-21 14:41:07 +0000[diff] [blame]23 int isa_bus;
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]24
Elyes HAOUAS8da96e52016-09-22 21:20:54 +0200[diff] [blame]25 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]26
Patrick Georgic8feedd2012-02-16 18:43:25 +0100[diff] [blame]27 mptable_init(mc, LOCAL_APIC_ADDR);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]28
Elyes HAOUAS8da96e52016-09-22 21:20:54 +0200[diff] [blame]29 smp_write_processors(mc);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]30
Patrick Georgi5244e1b2010-11-21 14:41:07 +0000[diff] [blame]31 mptable_write_buses(mc, NULL, &isa_bus);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]32
33 /* I/O APICs: APIC ID Version State Address */
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800[diff] [blame]34 smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]35
36 /* Legacy Interrupts */
37
Patrick Georgic5b87c82010-05-20 15:28:19 +0000[diff] [blame]38 mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]39
40 /* Builtin devices on Bus 0 */
41 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10);
42 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13);
43 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17);
44 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13);
45 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12);
46 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10);
47 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x10);
48 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x10);
49 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x11);
50
51 /* Firewire 4:0.0 */
52 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10);
53
54 /* Old riser card */
55 // riser slot top 5:8.0
56 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14);
57 // riser slot middle 5:9.0
58 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, 0x15);
59 // riser slot bottom 5:a.0
60 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16);
61
62 /* New Riser Card */
63 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x30, 0x2, 0x14);
64 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x34, 0x2, 0x15);
65 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x38, 0x2, 0x16);
66
67 /* Onboard Ethernet */
68 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
69
70 /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
Patrick Georgi6eb7a532011-10-07 21:42:52 +0200[diff] [blame]71 mptable_lintsrc(mc, isa_bus);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]72
73 /* Compute the checksums */
Patrick Georgib0a9c5c2011-10-07 23:01:55 +0200[diff] [blame]74 return mptable_finalize(mc);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]75}
76
77unsigned long write_smp_table(unsigned long addr)
78{
79 void *v;
Patrick Georgic75c79b2011-10-07 22:41:07 +0200[diff] [blame]80 v = smp_write_floating_table(addr, 0);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]81 return (unsigned long)smp_write_config_table(v);
82}