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review.coreboot.org / coreboot / 8da96e57c89860f429f1bf590c10fa364b8019d4 / . / src / mainboard / intel / d945gclf / mptable.c
blob: 342f1e6449986ef6fe04e47c49dea3524beff255 [file] [log] [blame]
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2008 coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
Uwe Hermann2d2f0c12009-10-28 17:36:11 +0000[diff] [blame]8 * published by the Free Software Foundation; version 2 of the License.
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]14 */
15
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]16#include <device/device.h>
17#include <device/pci.h>
18#include <console/console.h>
19#include <arch/smp/mpspec.h>
Uwe Hermann74d1a6e2010-10-12 17:34:08 +0000[diff] [blame]20#include <arch/ioapic.h>
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]21#include <string.h>
22#include <stdint.h>
23
Stefan Reinauer53b0ea42010-03-22 11:50:52 +0000[diff] [blame]24static void *smp_write_config_table(void *v)
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]25{
Elyes HAOUAS8da96e52016-09-22 21:20:54 +0200[diff] [blame^]26 struct mp_config_table *mc;
Patrick Georgi5244e1b2010-11-21 14:41:07 +0000[diff] [blame]27 int isa_bus;
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]28
Elyes HAOUAS8da96e52016-09-22 21:20:54 +0200[diff] [blame^]29 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]30
Patrick Georgic8feedd2012-02-16 18:43:25 +0100[diff] [blame]31 mptable_init(mc, LOCAL_APIC_ADDR);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]32
Elyes HAOUAS8da96e52016-09-22 21:20:54 +0200[diff] [blame^]33 smp_write_processors(mc);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]34
Patrick Georgi5244e1b2010-11-21 14:41:07 +0000[diff] [blame]35 mptable_write_buses(mc, NULL, &isa_bus);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]36
37 /* I/O APICs: APIC ID Version State Address */
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800[diff] [blame]38 smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]39
40 /* Legacy Interrupts */
41
Patrick Georgic5b87c82010-05-20 15:28:19 +0000[diff] [blame]42 mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]43
44 /* Builtin devices on Bus 0 */
45 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10);
46 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13);
47 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17);
48 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13);
49 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12);
50 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10);
51 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x10);
52 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x10);
53 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x11);
54
55 /* Firewire 4:0.0 */
56 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10);
57
58 /* Old riser card */
59 // riser slot top 5:8.0
60 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14);
61 // riser slot middle 5:9.0
62 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, 0x15);
63 // riser slot bottom 5:a.0
64 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16);
65
66 /* New Riser Card */
67 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x30, 0x2, 0x14);
68 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x34, 0x2, 0x15);
69 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x38, 0x2, 0x16);
70
71 /* Onboard Ethernet */
72 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
73
74 /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
Patrick Georgi6eb7a532011-10-07 21:42:52 +0200[diff] [blame]75 mptable_lintsrc(mc, isa_bus);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]76
77 /* Compute the checksums */
Patrick Georgib0a9c5c2011-10-07 23:01:55 +0200[diff] [blame]78 return mptable_finalize(mc);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]79}
80
81unsigned long write_smp_table(unsigned long addr)
82{
83 void *v;
Patrick Georgic75c79b2011-10-07 22:41:07 +0200[diff] [blame]84 v = smp_write_floating_table(addr, 0);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]85 return (unsigned long)smp_write_config_table(v);
86}