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review.coreboot.org / coreboot / b0a9c5ccf31514630755e9a5d15204a55a47740f / . / src / mainboard / intel / d945gclf / mptable.c
blob: ab537cb71822c92c0d99eb70fcc780b92425ff60 [file] [log] [blame]
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2008 coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
Uwe Hermann2d2f0c12009-10-28 17:36:11 +0000[diff] [blame]8 * published by the Free Software Foundation; version 2 of the License.
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
Uwe Hermann2d2f0c12009-10-28 17:36:11 +0000[diff] [blame]17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]18 */
19
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]20#include <device/device.h>
21#include <device/pci.h>
22#include <console/console.h>
23#include <arch/smp/mpspec.h>
Uwe Hermann74d1a6e2010-10-12 17:34:08 +0000[diff] [blame]24#include <arch/ioapic.h>
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]25#include <string.h>
26#include <stdint.h>
27
Stefan Reinauer53b0ea42010-03-22 11:50:52 +0000[diff] [blame]28static void *smp_write_config_table(void *v)
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]29{
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]30 struct mp_config_table *mc;
Patrick Georgi5244e1b2010-11-21 14:41:07 +0000[diff] [blame]31 int isa_bus;
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]32
33 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]34
Uwe Hermannc36d5062010-12-16 19:51:38 +0000[diff] [blame]35 mptable_init(mc, LAPIC_ADDR);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]36
37 smp_write_processors(mc);
38
Patrick Georgi5244e1b2010-11-21 14:41:07 +0000[diff] [blame]39 mptable_write_buses(mc, NULL, &isa_bus);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]40
41 /* I/O APICs: APIC ID Version State Address */
Uwe Hermann74d1a6e2010-10-12 17:34:08 +0000[diff] [blame]42 smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]43
44 /* Legacy Interrupts */
45
Patrick Georgic5b87c82010-05-20 15:28:19 +0000[diff] [blame]46 mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]47
48 /* Builtin devices on Bus 0 */
49 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10);
50 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13);
51 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17);
52 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13);
53 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12);
54 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10);
55 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x10);
56 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x10);
57 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x11);
58
59 /* Firewire 4:0.0 */
60 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10);
61
62 /* Old riser card */
63 // riser slot top 5:8.0
64 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14);
65 // riser slot middle 5:9.0
66 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, 0x15);
67 // riser slot bottom 5:a.0
68 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16);
69
70 /* New Riser Card */
71 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x30, 0x2, 0x14);
72 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x34, 0x2, 0x15);
73 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x38, 0x2, 0x16);
74
75 /* Onboard Ethernet */
76 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
77
78 /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
Patrick Georgi6eb7a532011-10-07 21:42:52 +0200[diff] [blame]79 mptable_lintsrc(mc, isa_bus);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]80
81 /* Compute the checksums */
Patrick Georgib0a9c5c2011-10-07 23:01:55 +0200[diff] [blame^]82 return mptable_finalize(mc);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]83}
84
85unsigned long write_smp_table(unsigned long addr)
86{
87 void *v;
Patrick Georgic75c79b2011-10-07 22:41:07 +0200[diff] [blame]88 v = smp_write_floating_table(addr, 0);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]89 return (unsigned long)smp_write_config_table(v);
90}