Patrick Georgi | 11f0079 | 2020-03-04 15:10:45 +0100 | [diff] [blame] | 1 | ## SPDX-License-Identifier: GPL-2.0-only |
Stefan Reinauer | 425b61e | 2015-03-15 04:29:35 +0100 | [diff] [blame] | 2 | |
Stefan Reinauer | a48ca84 | 2015-04-04 01:58:28 +0200 | [diff] [blame] | 3 | config ARCH_X86 |
| 4 | bool |
Stefan Reinauer | a48ca84 | 2015-04-04 01:58:28 +0200 | [diff] [blame] | 5 | select PCI |
Kyösti Mälkki | ec151f0 | 2018-06-03 22:48:51 +0300 | [diff] [blame] | 6 | select RELOCATABLE_MODULES |
Harshit Sharma | 65bec1c | 2020-08-05 22:25:27 -0700 | [diff] [blame] | 7 | select HAVE_ASAN_IN_RAMSTAGE |
Stefan Reinauer | a48ca84 | 2015-04-04 01:58:28 +0200 | [diff] [blame] | 8 | |
Angel Pons | 8e035e3 | 2021-06-22 12:58:20 +0200 | [diff] [blame] | 9 | if ARCH_X86 |
| 10 | |
Stefan Reinauer | 6867120 | 2015-03-15 04:34:03 +0100 | [diff] [blame] | 11 | # stage selectors for x86 |
| 12 | |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 13 | config ARCH_BOOTBLOCK_X86_32 |
Gabe Black | 5fbfc91 | 2013-07-07 13:52:37 -0700 | [diff] [blame] | 14 | bool |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 15 | |
Stefan Reinauer | 77b1655 | 2015-01-14 19:51:47 +0100 | [diff] [blame] | 16 | config ARCH_VERSTAGE_X86_32 |
| 17 | bool |
Stefan Reinauer | 77b1655 | 2015-01-14 19:51:47 +0100 | [diff] [blame] | 18 | |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 19 | config ARCH_ROMSTAGE_X86_32 |
| 20 | bool |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 21 | |
Patrick Georgi | 29eeece | 2018-10-31 14:24:47 +0100 | [diff] [blame] | 22 | config ARCH_POSTCAR_X86_32 |
| 23 | bool |
| 24 | default ARCH_ROMSTAGE_X86_32 && POSTCAR_STAGE |
| 25 | |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 26 | config ARCH_RAMSTAGE_X86_32 |
| 27 | bool |
Gabe Black | 5fbfc91 | 2013-07-07 13:52:37 -0700 | [diff] [blame] | 28 | |
Angel Pons | a32df26 | 2020-09-25 10:20:11 +0200 | [diff] [blame] | 29 | config ARCH_ALL_STAGES_X86_32 |
| 30 | bool |
Angel Pons | 6f5a658 | 2021-06-22 15:18:07 +0200 | [diff] [blame] | 31 | default ARCH_ALL_STAGES_X86 && !ARCH_ALL_STAGES_X86_64 |
Angel Pons | a32df26 | 2020-09-25 10:20:11 +0200 | [diff] [blame] | 32 | select ARCH_BOOTBLOCK_X86_32 |
| 33 | select ARCH_VERSTAGE_X86_32 |
| 34 | select ARCH_ROMSTAGE_X86_32 |
| 35 | select ARCH_RAMSTAGE_X86_32 |
Arthur Heymans | 5b528bc | 2022-03-24 10:38:54 +0100 | [diff] [blame^] | 36 | select ARCH_SUPPORTS_CLANG |
Angel Pons | a32df26 | 2020-09-25 10:20:11 +0200 | [diff] [blame] | 37 | |
Stefan Reinauer | 6867120 | 2015-03-15 04:34:03 +0100 | [diff] [blame] | 38 | # stage selectors for x64 |
| 39 | |
| 40 | config ARCH_BOOTBLOCK_X86_64 |
| 41 | bool |
Stefan Reinauer | 6867120 | 2015-03-15 04:34:03 +0100 | [diff] [blame] | 42 | |
| 43 | config ARCH_VERSTAGE_X86_64 |
| 44 | bool |
Stefan Reinauer | 6867120 | 2015-03-15 04:34:03 +0100 | [diff] [blame] | 45 | |
| 46 | config ARCH_ROMSTAGE_X86_64 |
| 47 | bool |
Stefan Reinauer | 6867120 | 2015-03-15 04:34:03 +0100 | [diff] [blame] | 48 | |
Patrick Georgi | 29eeece | 2018-10-31 14:24:47 +0100 | [diff] [blame] | 49 | config ARCH_POSTCAR_X86_64 |
| 50 | bool |
| 51 | default ARCH_ROMSTAGE_X86_64 && POSTCAR_STAGE |
| 52 | |
Stefan Reinauer | 6867120 | 2015-03-15 04:34:03 +0100 | [diff] [blame] | 53 | config ARCH_RAMSTAGE_X86_64 |
| 54 | bool |
Arthur Heymans | b86e96a | 2019-02-10 17:00:56 +0100 | [diff] [blame] | 55 | |
Angel Pons | 2db77907 | 2020-09-25 10:14:45 +0200 | [diff] [blame] | 56 | config ARCH_ALL_STAGES_X86_64 |
| 57 | bool |
| 58 | select ARCH_BOOTBLOCK_X86_64 |
| 59 | select ARCH_VERSTAGE_X86_64 |
| 60 | select ARCH_ROMSTAGE_X86_64 |
| 61 | select ARCH_RAMSTAGE_X86_64 |
| 62 | |
Angel Pons | 6f5a658 | 2021-06-22 15:18:07 +0200 | [diff] [blame] | 63 | config ARCH_ALL_STAGES_X86 |
| 64 | bool |
| 65 | default y |
| 66 | |
Angel Pons | 16fe5e1 | 2021-06-22 15:41:59 +0200 | [diff] [blame] | 67 | config HAVE_EXP_X86_64_SUPPORT |
| 68 | bool |
| 69 | help |
| 70 | Enable experimental support to build and run coreboot in 64-bit mode. |
| 71 | When selecting this option for a new platform, it is highly advisable |
| 72 | to provide a config file for Jenkins to build-test the 64-bit option. |
| 73 | |
| 74 | config USE_EXP_X86_64_SUPPORT |
| 75 | bool "[EXPERIMENTAL] Run coreboot in long (64-bit) mode" |
| 76 | depends on HAVE_EXP_X86_64_SUPPORT |
| 77 | select ARCH_ALL_STAGES_X86_64 |
| 78 | help |
| 79 | When set, most of coreboot runs in long (64-bit) mode instead of the |
| 80 | usual protected flat (32-bit) mode. 64-bit CPUs and OSes can be used |
| 81 | irrespective of whether coreboot runs in 32-bit or 64-bit mode. This |
| 82 | is an experimental option: do not enable unless one wants to test it |
| 83 | and has the means to recover a system when coreboot fails to boot. |
| 84 | |
Patrick Rudolph | b1ef725 | 2019-09-28 17:44:01 +0200 | [diff] [blame] | 85 | config ARCH_X86_64_PGTBL_LOC |
| 86 | hex "x86_64 page table location in CBFS" |
| 87 | depends on ARCH_BOOTBLOCK_X86_64 |
Patrick Rudolph | 19a60a4 | 2019-11-30 09:40:52 +0100 | [diff] [blame] | 88 | default 0xfffe9000 |
Patrick Rudolph | b1ef725 | 2019-09-28 17:44:01 +0200 | [diff] [blame] | 89 | help |
| 90 | The position where to place pagetables. Needs to be known at |
| 91 | compile time. Must not overlap other files in CBFS. |
| 92 | |
Martin Roth | 0cd9ff8 | 2016-02-01 17:33:37 -0700 | [diff] [blame] | 93 | config USE_MARCH_586 |
| 94 | def_bool n |
| 95 | help |
| 96 | Allow a platform or processor to select to be compiled using |
| 97 | the '-march=i586' option instead of the typical '-march=i686' |
| 98 | |
Uwe Hermann | 168b11b | 2009-10-07 16:15:40 +0000 | [diff] [blame] | 99 | # This is an SMP option. It relates to starting up APs. |
| 100 | # It is usually set in mainboard/*/Kconfig. |
| 101 | # TODO: Improve description. |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 102 | config AP_IN_SIPI_WAIT |
| 103 | bool |
| 104 | default n |
Stefan Reinauer | 2a6f390 | 2012-10-15 13:38:09 -0700 | [diff] [blame] | 105 | depends on ARCH_X86 && SMP |
Ronald G. Minnich | 6ed39d9 | 2009-08-29 02:59:35 +0000 | [diff] [blame] | 106 | |
Martin Roth | 8418fd4 | 2019-04-22 16:26:23 -0600 | [diff] [blame] | 107 | config RESET_VECTOR_IN_RAM |
| 108 | bool |
| 109 | depends on ARCH_X86 |
Felix Held | ca928c6 | 2020-04-04 01:47:37 +0200 | [diff] [blame] | 110 | select NO_XIP_EARLY_STAGES |
Martin Roth | 8418fd4 | 2019-04-22 16:26:23 -0600 | [diff] [blame] | 111 | help |
Felix Held | ca928c6 | 2020-04-04 01:47:37 +0200 | [diff] [blame] | 112 | Select this option if the x86 processor's reset vector is in |
| 113 | preinitialized DRAM instead of the traditional 0xfffffff0 location. |
Martin Roth | 8418fd4 | 2019-04-22 16:26:23 -0600 | [diff] [blame] | 114 | |
Kyösti Mälkki | f8c7c23 | 2012-04-06 04:03:50 +0300 | [diff] [blame] | 115 | # Aligns 16bit entry code in bootblock so that hyper-threading CPUs |
| 116 | # can boot AP CPUs to enable their shared caches. |
| 117 | config SIPI_VECTOR_IN_ROM |
| 118 | bool |
| 119 | default n |
| 120 | depends on ARCH_X86 |
| 121 | |
Alexandru Gagniuc | 6a62231 | 2015-10-27 10:27:30 -0700 | [diff] [blame] | 122 | # Traditionally BIOS region on SPI flash boot media was memory mapped right below |
| 123 | # 4G and it was the last region in the IFD. This way translation between CPU |
| 124 | # address space to flash address was trivial. However some IFDs on newer SoCs |
Raul E Rangel | e92a982 | 2021-06-24 16:54:27 -0600 | [diff] [blame] | 125 | # have BIOS region sandwiched between descriptor and other regions. Turning on |
| 126 | # X86_CUSTOM_BOOTMEDIA disables X86_TOP4G_BOOTMEDIA_MAP which allows the |
| 127 | # soc code to provide custom mmap_boot.c. |
| 128 | config X86_CUSTOM_BOOTMEDIA |
| 129 | bool |
| 130 | |
Alexandru Gagniuc | 6a62231 | 2015-10-27 10:27:30 -0700 | [diff] [blame] | 131 | config X86_TOP4G_BOOTMEDIA_MAP |
| 132 | bool |
Raul E Rangel | e92a982 | 2021-06-24 16:54:27 -0600 | [diff] [blame] | 133 | depends on !X86_CUSTOM_BOOTMEDIA |
Alexandru Gagniuc | 6a62231 | 2015-10-27 10:27:30 -0700 | [diff] [blame] | 134 | default y |
| 135 | |
Ronald G. Minnich | b5e777c | 2013-07-22 20:17:18 +0200 | [diff] [blame] | 136 | # This is something you almost certainly don't want to mess with. |
| 137 | # How many SIPIs do we send when starting up APs and cores? |
| 138 | # The answer in 2000 or so was '2'. Nowadays, on many systems, |
| 139 | # it is 1. Set a safe default here, and you can override it |
| 140 | # on reasonable platforms. |
| 141 | config NUM_IPI_STARTS |
| 142 | int |
| 143 | default 2 |
| 144 | |
Naresh G Solanki | 04bb480 | 2016-12-13 21:16:46 +0530 | [diff] [blame] | 145 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 146 | hex |
| 147 | default 0xc00 |
| 148 | help |
| 149 | Increase this value if preram cbmem console is getting truncated |
| 150 | |
Julius Werner | baf27db | 2019-10-02 17:28:56 -0700 | [diff] [blame] | 151 | config CBFS_MCACHE_SIZE |
| 152 | hex |
| 153 | depends on !NO_CBFS_MCACHE |
Julius Werner | 40acfe7 | 2021-05-12 15:59:58 -0700 | [diff] [blame] | 154 | default 0x4000 |
Julius Werner | baf27db | 2019-10-02 17:28:56 -0700 | [diff] [blame] | 155 | help |
Julius Werner | 40acfe7 | 2021-05-12 15:59:58 -0700 | [diff] [blame] | 156 | Increase this value if you see CBFS mcache overflow warnings. Do NOT |
| 157 | change this value for vboot RW updates! |
Julius Werner | baf27db | 2019-10-02 17:28:56 -0700 | [diff] [blame] | 158 | |
Stefan Reinauer | 8aedcbc | 2010-12-16 23:37:17 +0000 | [diff] [blame] | 159 | config PC80_SYSTEM |
| 160 | bool |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 161 | default y if ARCH_X86 |
Stefan Reinauer | 8aedcbc | 2010-12-16 23:37:17 +0000 | [diff] [blame] | 162 | |
Lee Leahy | fdc8c8b | 2016-06-07 08:45:17 -0700 | [diff] [blame] | 163 | config BOOTBLOCK_DEBUG_SPINLOOP |
| 164 | bool |
| 165 | default n |
| 166 | help |
| 167 | Add a spin (JMP .) in bootblock_crt0.S during early bootblock to wait |
| 168 | for a JTAG debugger to break into the execution sequence. |
| 169 | |
Patrick Georgi | a865b17 | 2011-01-14 07:40:24 +0000 | [diff] [blame] | 170 | config HAVE_CMOS_DEFAULT |
| 171 | def_bool n |
Martin Roth | f76303e | 2016-11-16 15:45:22 -0700 | [diff] [blame] | 172 | depends on HAVE_OPTION_TABLE |
Patrick Georgi | a865b17 | 2011-01-14 07:40:24 +0000 | [diff] [blame] | 173 | |
| 174 | config CMOS_DEFAULT_FILE |
| 175 | string |
Patrick Georgi | b8fba86 | 2020-06-17 21:06:53 +0200 | [diff] [blame] | 176 | default "src/mainboard/\$(MAINBOARDDIR)/cmos.default" |
Patrick Georgi | a865b17 | 2011-01-14 07:40:24 +0000 | [diff] [blame] | 177 | depends on HAVE_CMOS_DEFAULT |
| 178 | |
Felix Held | 4e03727 | 2022-02-23 16:35:58 +0100 | [diff] [blame] | 179 | config HPET_MIN_TICKS |
| 180 | hex |
| 181 | |
Aaron Durbin | 65ac3d8 | 2016-02-11 14:36:19 -0600 | [diff] [blame] | 182 | config C_ENV_BOOTBLOCK_SIZE |
| 183 | hex |
Kyösti Mälkki | e76ce87 | 2020-05-25 08:52:07 +0300 | [diff] [blame] | 184 | default 0x40000 if !FIXED_BOOTBLOCK_SIZE |
| 185 | help |
| 186 | This is only the default maximum of bootblock size for linking |
| 187 | purposes. Platforms may provide different limit and need to |
| 188 | specify this when FIXED_BOOTBLOCK_SIZE is selected. |
Andrey Petrov | ccd300b | 2016-02-28 22:04:51 -0800 | [diff] [blame] | 189 | |
Kyösti Mälkki | 49dbbe9 | 2019-12-21 10:17:56 +0200 | [diff] [blame] | 190 | config FIXED_BOOTBLOCK_SIZE |
| 191 | bool |
| 192 | |
Andrey Petrov | ccd300b | 2016-02-28 22:04:51 -0800 | [diff] [blame] | 193 | # Default address romstage is to be linked at |
| 194 | config ROMSTAGE_ADDR |
| 195 | hex |
| 196 | default 0x2000000 |
| 197 | |
| 198 | # Default address verstage is to be linked at |
| 199 | config VERSTAGE_ADDR |
| 200 | hex |
| 201 | default 0x2000000 |
Aaron Durbin | 7f8afe0 | 2016-03-18 12:21:23 -0500 | [diff] [blame] | 202 | |
| 203 | # Use the post CAR infrastructure for tearing down cache-as-ram |
Elyes HAOUAS | 777ea89 | 2016-07-29 07:40:41 +0200 | [diff] [blame] | 204 | # from a program loaded in RAM and subsequently loading ramstage. |
Aaron Durbin | 7f8afe0 | 2016-03-18 12:21:23 -0500 | [diff] [blame] | 205 | config POSTCAR_STAGE |
Kyösti Mälkki | 0f5e01a | 2019-08-09 07:11:07 +0300 | [diff] [blame] | 206 | def_bool y |
| 207 | depends on ARCH_X86 |
Felix Held | ca928c6 | 2020-04-04 01:47:37 +0200 | [diff] [blame] | 208 | depends on !RESET_VECTOR_IN_RAM |
Lee Leahy | d131ea3 | 2016-06-08 13:40:08 -0700 | [diff] [blame] | 209 | |
| 210 | config VERSTAGE_DEBUG_SPINLOOP |
| 211 | bool |
| 212 | default n |
| 213 | help |
| 214 | Add a spin (JMP .) in assembly_entry.S during early verstage to wait |
| 215 | for a JTAG debugger to break into the execution sequence. |
| 216 | |
| 217 | config ROMSTAGE_DEBUG_SPINLOOP |
| 218 | bool |
| 219 | default n |
| 220 | help |
| 221 | Add a spin (JMP .) in assembly_entry.S during early romstage to wait |
| 222 | for a JTAG debugger to break into the execution sequence. |
Martin Roth | 408fda7 | 2016-12-15 16:04:55 -0700 | [diff] [blame] | 223 | |
| 224 | choice |
| 225 | prompt "Bootblock behaviour" |
| 226 | default BOOTBLOCK_SIMPLE |
Kyösti Mälkki | b8d575c | 2019-12-16 16:00:49 +0200 | [diff] [blame] | 227 | depends on !VBOOT |
Martin Roth | 408fda7 | 2016-12-15 16:04:55 -0700 | [diff] [blame] | 228 | |
| 229 | config BOOTBLOCK_SIMPLE |
| 230 | bool "Always load fallback" |
| 231 | |
| 232 | config BOOTBLOCK_NORMAL |
Arthur Heymans | 6f75154 | 2019-06-08 11:28:52 +0200 | [diff] [blame] | 233 | select CONFIGURABLE_CBFS_PREFIX |
Martin Roth | 408fda7 | 2016-12-15 16:04:55 -0700 | [diff] [blame] | 234 | bool "Switch to normal if CMOS says so" |
| 235 | |
| 236 | endchoice |
| 237 | |
Martin Roth | 408fda7 | 2016-12-15 16:04:55 -0700 | [diff] [blame] | 238 | config SKIP_MAX_REBOOT_CNT_CLEAR |
| 239 | bool "Do not clear reboot count after successful boot" |
| 240 | depends on BOOTBLOCK_NORMAL |
| 241 | help |
| 242 | Do not clear the reboot count immediately after successful boot. |
| 243 | Set to allow the payload to control normal/fallback image recovery. |
| 244 | Note that it is the responsibility of the payload to reset the |
Paul Menzel | b949902 | 2019-01-08 16:21:31 +0100 | [diff] [blame] | 245 | normal boot bit to 1 after each successful boot. |
Marc Jones | 7a2d4ea | 2017-08-25 18:54:23 -0600 | [diff] [blame] | 246 | |
Furquan Shaikh | bf4b7b0 | 2020-04-30 18:08:16 -0700 | [diff] [blame] | 247 | config ACPI_BERT |
Nico Huber | 9df72e0 | 2018-11-24 18:25:50 +0100 | [diff] [blame] | 248 | bool |
Marc Jones | 7a2d4ea | 2017-08-25 18:54:23 -0600 | [diff] [blame] | 249 | depends on HAVE_ACPI_TABLES |
| 250 | help |
Furquan Shaikh | bf4b7b0 | 2020-04-30 18:08:16 -0700 | [diff] [blame] | 251 | Build an ACPI Boot Error Record Table. |
Aaron Durbin | f49ddb6 | 2018-01-24 17:35:58 -0700 | [diff] [blame] | 252 | |
| 253 | config COLLECT_TIMESTAMPS_NO_TSC |
| 254 | bool |
| 255 | default n |
| 256 | depends on COLLECT_TIMESTAMPS |
| 257 | help |
| 258 | Use a non-TSC platform-dependent source for timestamps. |
| 259 | |
| 260 | config COLLECT_TIMESTAMPS_TSC |
| 261 | bool |
| 262 | default y if !COLLECT_TIMESTAMPS_NO_TSC |
| 263 | default n |
| 264 | depends on COLLECT_TIMESTAMPS |
| 265 | help |
| 266 | Use the TSC as the timestamp source. |
Aaron Durbin | 0f35af8f | 2018-04-18 01:00:27 -0600 | [diff] [blame] | 267 | |
| 268 | config PAGING_IN_CACHE_AS_RAM |
| 269 | bool |
| 270 | default n |
| 271 | depends on ARCH_X86 |
| 272 | help |
| 273 | Chipsets scan select this option to preallocate area in cache-as-ram |
| 274 | for storing paging data structures. PAE paging is currently the |
| 275 | only thing being supported. |
| 276 | |
| 277 | config NUM_CAR_PAGE_TABLE_PAGES |
| 278 | int |
| 279 | default 5 |
| 280 | depends on PAGING_IN_CACHE_AS_RAM |
| 281 | help |
| 282 | The number of 4KiB pages that should be pre-allocated for page tables. |
Aaron Durbin | 4b032e4 | 2018-04-20 01:39:30 -0600 | [diff] [blame] | 283 | |
| 284 | # Provide the interrupt handlers to every stage. Not all |
| 285 | # stages may take advantage. |
| 286 | config IDT_IN_EVERY_STAGE |
| 287 | bool |
| 288 | default n |
| 289 | depends on ARCH_X86 |
Nico Huber | 33fcaf9 | 2018-10-10 22:44:20 +0200 | [diff] [blame] | 290 | |
| 291 | config HAVE_CF9_RESET |
| 292 | bool |
| 293 | |
| 294 | config HAVE_CF9_RESET_PREPARE |
| 295 | bool |
| 296 | depends on HAVE_CF9_RESET |
Kyösti Mälkki | b72b5d9 | 2019-07-04 21:08:17 +0300 | [diff] [blame] | 297 | |
| 298 | config PIRQ_ROUTE |
| 299 | bool |
| 300 | default n |
| 301 | |
| 302 | config MAX_PIRQ_LINKS |
| 303 | int |
| 304 | default 4 |
| 305 | depends on PIRQ_ROUTE |
| 306 | help |
| 307 | This variable specifies the number of PIRQ interrupt links which are |
| 308 | routable. On most chipsets, this is 4, INTA through INTD. Some |
| 309 | chipsets offer more than four links, commonly up to INTH. They may |
| 310 | also have a separate link for ATA or IOAPIC interrupts. When the PIRQ |
| 311 | table specifies links greater than 4, pirq_route_irqs will not |
| 312 | function properly, unless this variable is correctly set. |
Arthur Heymans | b86e96a | 2019-02-10 17:00:56 +0100 | [diff] [blame] | 313 | |
Duncan Laurie | f02bf35 | 2020-03-17 18:32:54 -0700 | [diff] [blame] | 314 | config MAX_ACPI_TABLE_SIZE_KB |
| 315 | int |
| 316 | default 144 |
| 317 | help |
| 318 | Set the maximum size of all ACPI tables in KiB. |
| 319 | |
Furquan Shaikh | 46514c2 | 2020-06-11 11:59:07 -0700 | [diff] [blame] | 320 | config MEMLAYOUT_LD_FILE |
| 321 | string |
| 322 | default "src/arch/x86/memlayout.ld" |
| 323 | |
Robert Zieba | 3f01cd1 | 2022-04-14 10:36:15 -0600 | [diff] [blame] | 324 | config DEBUG_HW_BREAKPOINTS |
| 325 | bool |
| 326 | default y |
| 327 | help |
| 328 | Enable support for hardware data and instruction breakpoints through |
| 329 | the x86 debug registers |
| 330 | |
| 331 | config DEBUG_HW_BREAKPOINTS_IN_ALL_STAGES |
| 332 | bool |
| 333 | default y |
| 334 | depends on DEBUG_HW_BREAKPOINTS && IDT_IN_EVERY_STAGE |
| 335 | |
| 336 | config DEBUG_NULL_DEREF_BREAKPOINTS |
| 337 | bool |
| 338 | default y |
| 339 | depends on DEBUG_HW_BREAKPOINTS |
| 340 | help |
| 341 | Enable support for catching null dereferences and instruction execution |
| 342 | |
| 343 | config DEBUG_NULL_DEREF_BREAKPOINTS_IN_ALL_STAGES |
| 344 | bool |
| 345 | default y |
| 346 | depends on DEBUG_NULL_DEREF_BREAKPOINTS && DEBUG_HW_BREAKPOINTS_IN_ALL_STAGES |
| 347 | |
| 348 | config DEBUG_NULL_DEREF_HALT |
| 349 | bool |
| 350 | default n |
| 351 | depends on DEBUG_NULL_DEREF_BREAKPOINTS |
| 352 | help |
| 353 | When enabled null dereferences and instruction fetches will halt execution. |
| 354 | Otherwise an error will be printed. |
| 355 | |
Bill XIE | f0215b4 | 2021-03-20 21:06:11 +0800 | [diff] [blame] | 356 | # Some EC need an "EC firmware pointer" (a data structure hinting the address |
| 357 | # of its firmware blobs) being put at a fixed position. Its space |
| 358 | # (__section__(".ecfw_ptr")) should be reserved if it lies in the range of a |
| 359 | # stage. Different EC may have different format and/or value for it. The actual |
| 360 | # address of EC firmware pointer should be provided in the Kconfig of the EC |
| 361 | # requiring it, and its value could be filled by linking a read-only global |
| 362 | # data object to the section above. |
| 363 | |
| 364 | config ECFW_PTR_ADDR |
| 365 | hex |
| 366 | help |
| 367 | Address of reserved space for EC firmware pointer, which should not |
| 368 | overlap other data such as reset vector or FIT pointer if present. |
| 369 | |
| 370 | config ECFW_PTR_SIZE |
| 371 | int |
| 372 | help |
| 373 | Size of reserved space for EC firmware pointer |
| 374 | |
Arthur Heymans | b86e96a | 2019-02-10 17:00:56 +0100 | [diff] [blame] | 375 | endif |