Patrick Georgi | 11f0079 | 2020-03-04 15:10:45 +0100 | [diff] [blame] | 1 | ## SPDX-License-Identifier: GPL-2.0-only |
Stefan Reinauer | 425b61e | 2015-03-15 04:29:35 +0100 | [diff] [blame] | 2 | |
Stefan Reinauer | a48ca84 | 2015-04-04 01:58:28 +0200 | [diff] [blame] | 3 | config ARCH_X86 |
| 4 | bool |
Stefan Reinauer | a48ca84 | 2015-04-04 01:58:28 +0200 | [diff] [blame] | 5 | select PCI |
Kyösti Mälkki | ec151f0 | 2018-06-03 22:48:51 +0300 | [diff] [blame] | 6 | select RELOCATABLE_MODULES |
Harshit Sharma | 65bec1c | 2020-08-05 22:25:27 -0700 | [diff] [blame] | 7 | select HAVE_ASAN_IN_RAMSTAGE |
Elyes Haouas | b6efe17 | 2024-03-03 17:41:34 +0100 | [diff] [blame] | 8 | select ARCH_SUPPORTS_CLANG |
Stefan Reinauer | a48ca84 | 2015-04-04 01:58:28 +0200 | [diff] [blame] | 9 | |
Angel Pons | 8e035e3 | 2021-06-22 12:58:20 +0200 | [diff] [blame] | 10 | if ARCH_X86 |
| 11 | |
Stefan Reinauer | 6867120 | 2015-03-15 04:34:03 +0100 | [diff] [blame] | 12 | # stage selectors for x86 |
| 13 | |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 14 | config ARCH_BOOTBLOCK_X86_32 |
Gabe Black | 5fbfc91 | 2013-07-07 13:52:37 -0700 | [diff] [blame] | 15 | bool |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 16 | |
Stefan Reinauer | 77b1655 | 2015-01-14 19:51:47 +0100 | [diff] [blame] | 17 | config ARCH_VERSTAGE_X86_32 |
| 18 | bool |
Stefan Reinauer | 77b1655 | 2015-01-14 19:51:47 +0100 | [diff] [blame] | 19 | |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 20 | config ARCH_ROMSTAGE_X86_32 |
| 21 | bool |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 22 | |
Patrick Georgi | 29eeece | 2018-10-31 14:24:47 +0100 | [diff] [blame] | 23 | config ARCH_POSTCAR_X86_32 |
| 24 | bool |
| 25 | default ARCH_ROMSTAGE_X86_32 && POSTCAR_STAGE |
| 26 | |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 27 | config ARCH_RAMSTAGE_X86_32 |
| 28 | bool |
Gabe Black | 5fbfc91 | 2013-07-07 13:52:37 -0700 | [diff] [blame] | 29 | |
Angel Pons | a32df26 | 2020-09-25 10:20:11 +0200 | [diff] [blame] | 30 | config ARCH_ALL_STAGES_X86_32 |
| 31 | bool |
Arthur Heymans | 6e85740 | 2022-11-12 16:16:02 +0100 | [diff] [blame] | 32 | default !ARCH_ALL_STAGES_X86_64 |
Angel Pons | a32df26 | 2020-09-25 10:20:11 +0200 | [diff] [blame] | 33 | select ARCH_BOOTBLOCK_X86_32 |
Arthur Heymans | 6e85740 | 2022-11-12 16:16:02 +0100 | [diff] [blame] | 34 | select ARCH_VERSTAGE_X86_32 if !VBOOT_STARTS_BEFORE_BOOTBLOCK |
Angel Pons | a32df26 | 2020-09-25 10:20:11 +0200 | [diff] [blame] | 35 | select ARCH_ROMSTAGE_X86_32 |
| 36 | select ARCH_RAMSTAGE_X86_32 |
| 37 | |
Stefan Reinauer | 6867120 | 2015-03-15 04:34:03 +0100 | [diff] [blame] | 38 | # stage selectors for x64 |
| 39 | |
| 40 | config ARCH_BOOTBLOCK_X86_64 |
| 41 | bool |
Patrick Rudolph | e249b1a | 2020-08-27 21:07:57 +0200 | [diff] [blame] | 42 | select SSE2 |
Stefan Reinauer | 6867120 | 2015-03-15 04:34:03 +0100 | [diff] [blame] | 43 | |
| 44 | config ARCH_VERSTAGE_X86_64 |
| 45 | bool |
Patrick Rudolph | e249b1a | 2020-08-27 21:07:57 +0200 | [diff] [blame] | 46 | select SSE2 |
Stefan Reinauer | 6867120 | 2015-03-15 04:34:03 +0100 | [diff] [blame] | 47 | |
| 48 | config ARCH_ROMSTAGE_X86_64 |
| 49 | bool |
Patrick Rudolph | e249b1a | 2020-08-27 21:07:57 +0200 | [diff] [blame] | 50 | select SSE2 |
Stefan Reinauer | 6867120 | 2015-03-15 04:34:03 +0100 | [diff] [blame] | 51 | |
Patrick Georgi | 29eeece | 2018-10-31 14:24:47 +0100 | [diff] [blame] | 52 | config ARCH_POSTCAR_X86_64 |
| 53 | bool |
| 54 | default ARCH_ROMSTAGE_X86_64 && POSTCAR_STAGE |
Patrick Rudolph | e249b1a | 2020-08-27 21:07:57 +0200 | [diff] [blame] | 55 | select SSE2 |
Patrick Georgi | 29eeece | 2018-10-31 14:24:47 +0100 | [diff] [blame] | 56 | |
Stefan Reinauer | 6867120 | 2015-03-15 04:34:03 +0100 | [diff] [blame] | 57 | config ARCH_RAMSTAGE_X86_64 |
| 58 | bool |
Patrick Rudolph | e249b1a | 2020-08-27 21:07:57 +0200 | [diff] [blame] | 59 | select SSE2 |
Arthur Heymans | b86e96a | 2019-02-10 17:00:56 +0100 | [diff] [blame] | 60 | |
Angel Pons | 2db77907 | 2020-09-25 10:14:45 +0200 | [diff] [blame] | 61 | config ARCH_ALL_STAGES_X86_64 |
| 62 | bool |
| 63 | select ARCH_BOOTBLOCK_X86_64 |
Arthur Heymans | 6e85740 | 2022-11-12 16:16:02 +0100 | [diff] [blame] | 64 | select ARCH_VERSTAGE_X86_64 if !VBOOT_STARTS_BEFORE_BOOTBLOCK |
Angel Pons | 2db77907 | 2020-09-25 10:14:45 +0200 | [diff] [blame] | 65 | select ARCH_ROMSTAGE_X86_64 |
| 66 | select ARCH_RAMSTAGE_X86_64 |
| 67 | |
Arthur Heymans | d293b20 | 2024-02-02 19:35:13 +0100 | [diff] [blame] | 68 | config HAVE_X86_64_SUPPORT |
Angel Pons | 16fe5e1 | 2021-06-22 15:41:59 +0200 | [diff] [blame] | 69 | bool |
| 70 | help |
| 71 | Enable experimental support to build and run coreboot in 64-bit mode. |
| 72 | When selecting this option for a new platform, it is highly advisable |
| 73 | to provide a config file for Jenkins to build-test the 64-bit option. |
| 74 | |
Arthur Heymans | d293b20 | 2024-02-02 19:35:13 +0100 | [diff] [blame] | 75 | config USE_X86_64_SUPPORT |
| 76 | bool "Run coreboot in long (64-bit) mode" |
| 77 | depends on HAVE_X86_64_SUPPORT |
Angel Pons | 16fe5e1 | 2021-06-22 15:41:59 +0200 | [diff] [blame] | 78 | select ARCH_ALL_STAGES_X86_64 |
| 79 | help |
| 80 | When set, most of coreboot runs in long (64-bit) mode instead of the |
| 81 | usual protected flat (32-bit) mode. 64-bit CPUs and OSes can be used |
Arthur Heymans | d293b20 | 2024-02-02 19:35:13 +0100 | [diff] [blame] | 82 | irrespective of whether coreboot runs in 32-bit or 64-bit mode. |
Angel Pons | 16fe5e1 | 2021-06-22 15:41:59 +0200 | [diff] [blame] | 83 | |
Arthur Heymans | ee83be4 | 2024-02-02 18:49:53 +0100 | [diff] [blame] | 84 | config PAGE_TABLES_IN_CBFS |
| 85 | bool |
| 86 | default n |
| 87 | |
Patrick Rudolph | b1ef725 | 2019-09-28 17:44:01 +0200 | [diff] [blame] | 88 | config ARCH_X86_64_PGTBL_LOC |
| 89 | hex "x86_64 page table location in CBFS" |
Arthur Heymans | ee83be4 | 2024-02-02 18:49:53 +0100 | [diff] [blame] | 90 | depends on ARCH_BOOTBLOCK_X86_64 && PAGE_TABLES_IN_CBFS |
Patrick Rudolph | 19a60a4 | 2019-11-30 09:40:52 +0100 | [diff] [blame] | 91 | default 0xfffe9000 |
Patrick Rudolph | b1ef725 | 2019-09-28 17:44:01 +0200 | [diff] [blame] | 92 | help |
| 93 | The position where to place pagetables. Needs to be known at |
| 94 | compile time. Must not overlap other files in CBFS. |
| 95 | |
Felix Held | 3748fca | 2023-09-12 14:48:38 +0200 | [diff] [blame] | 96 | config RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT |
| 97 | bool |
| 98 | help |
| 99 | On some systems, the upper physical address bits are reserved and |
| 100 | used as a tag which is typically related to a memory encryption |
| 101 | feature. When selecting this option, the SoC code needs to implement |
| 102 | get_reserved_phys_addr_bits so that the common code knows how many of |
| 103 | the most significant physical address bits are reserved and can't be |
| 104 | used as address bits. |
| 105 | |
Uwe Hermann | 168b11b | 2009-10-07 16:15:40 +0000 | [diff] [blame] | 106 | # This is an SMP option. It relates to starting up APs. |
| 107 | # It is usually set in mainboard/*/Kconfig. |
| 108 | # TODO: Improve description. |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 109 | config AP_IN_SIPI_WAIT |
| 110 | bool |
| 111 | default n |
Stefan Reinauer | 2a6f390 | 2012-10-15 13:38:09 -0700 | [diff] [blame] | 112 | depends on ARCH_X86 && SMP |
Ronald G. Minnich | 6ed39d9 | 2009-08-29 02:59:35 +0000 | [diff] [blame] | 113 | |
Martin Roth | 8418fd4 | 2019-04-22 16:26:23 -0600 | [diff] [blame] | 114 | config RESET_VECTOR_IN_RAM |
| 115 | bool |
| 116 | depends on ARCH_X86 |
Felix Held | ca928c6 | 2020-04-04 01:47:37 +0200 | [diff] [blame] | 117 | select NO_XIP_EARLY_STAGES |
Martin Roth | 8418fd4 | 2019-04-22 16:26:23 -0600 | [diff] [blame] | 118 | help |
Felix Held | ca928c6 | 2020-04-04 01:47:37 +0200 | [diff] [blame] | 119 | Select this option if the x86 processor's reset vector is in |
| 120 | preinitialized DRAM instead of the traditional 0xfffffff0 location. |
Martin Roth | 8418fd4 | 2019-04-22 16:26:23 -0600 | [diff] [blame] | 121 | |
Kyösti Mälkki | f8c7c23 | 2012-04-06 04:03:50 +0300 | [diff] [blame] | 122 | # Aligns 16bit entry code in bootblock so that hyper-threading CPUs |
| 123 | # can boot AP CPUs to enable their shared caches. |
| 124 | config SIPI_VECTOR_IN_ROM |
| 125 | bool |
| 126 | default n |
| 127 | depends on ARCH_X86 |
| 128 | |
Alexandru Gagniuc | 6a62231 | 2015-10-27 10:27:30 -0700 | [diff] [blame] | 129 | # Traditionally BIOS region on SPI flash boot media was memory mapped right below |
| 130 | # 4G and it was the last region in the IFD. This way translation between CPU |
| 131 | # address space to flash address was trivial. However some IFDs on newer SoCs |
Raul E Rangel | e92a982 | 2021-06-24 16:54:27 -0600 | [diff] [blame] | 132 | # have BIOS region sandwiched between descriptor and other regions. Turning on |
| 133 | # X86_CUSTOM_BOOTMEDIA disables X86_TOP4G_BOOTMEDIA_MAP which allows the |
| 134 | # soc code to provide custom mmap_boot.c. |
| 135 | config X86_CUSTOM_BOOTMEDIA |
| 136 | bool |
| 137 | |
Alexandru Gagniuc | 6a62231 | 2015-10-27 10:27:30 -0700 | [diff] [blame] | 138 | config X86_TOP4G_BOOTMEDIA_MAP |
| 139 | bool |
Raul E Rangel | e92a982 | 2021-06-24 16:54:27 -0600 | [diff] [blame] | 140 | depends on !X86_CUSTOM_BOOTMEDIA |
Alexandru Gagniuc | 6a62231 | 2015-10-27 10:27:30 -0700 | [diff] [blame] | 141 | default y |
| 142 | |
Naresh G Solanki | 04bb480 | 2016-12-13 21:16:46 +0530 | [diff] [blame] | 143 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 144 | hex |
| 145 | default 0xc00 |
| 146 | help |
| 147 | Increase this value if preram cbmem console is getting truncated |
| 148 | |
Julius Werner | baf27db | 2019-10-02 17:28:56 -0700 | [diff] [blame] | 149 | config CBFS_MCACHE_SIZE |
| 150 | hex |
| 151 | depends on !NO_CBFS_MCACHE |
Julius Werner | 40acfe7 | 2021-05-12 15:59:58 -0700 | [diff] [blame] | 152 | default 0x4000 |
Julius Werner | baf27db | 2019-10-02 17:28:56 -0700 | [diff] [blame] | 153 | help |
Julius Werner | 40acfe7 | 2021-05-12 15:59:58 -0700 | [diff] [blame] | 154 | Increase this value if you see CBFS mcache overflow warnings. Do NOT |
| 155 | change this value for vboot RW updates! |
Julius Werner | baf27db | 2019-10-02 17:28:56 -0700 | [diff] [blame] | 156 | |
Jeremy Compostella | 052fb7c | 2023-08-18 14:25:22 -0700 | [diff] [blame] | 157 | config PRERAM_CBFS_CACHE_SIZE |
| 158 | hex |
| 159 | default 0x4000 |
| 160 | help |
| 161 | Define the size of the Pre-RAM stages CBFS cache. A size of |
| 162 | zero disables the CBFS cache feature in pre-memory stages. |
| 163 | |
Jeremy Compostella | 226f51c | 2023-10-12 09:40:12 -0700 | [diff] [blame] | 164 | config POSTRAM_CBFS_CACHE_IN_BSS |
| 165 | bool |
| 166 | default y if !SOC_AMD_COMMON_BLOCK_NONCAR |
| 167 | help |
| 168 | Allocate the post-memory CBFS cache scratchpad in the .bss |
| 169 | section. CBFS cache will rely on a simple static C buffer |
| 170 | while traditionally CBFS cache memory region is reserved in |
| 171 | the device memory layout. |
| 172 | |
| 173 | config RAMSTAGE_CBFS_CACHE_SIZE |
| 174 | hex |
| 175 | default 0x4000 |
| 176 | depends on POSTRAM_CBFS_CACHE_IN_BSS |
| 177 | help |
| 178 | Define the size of the ramstage CBFS cache. A size of zero |
| 179 | disables the CBFS cache feature in ramstage. |
| 180 | |
Stefan Reinauer | 8aedcbc | 2010-12-16 23:37:17 +0000 | [diff] [blame] | 181 | config PC80_SYSTEM |
| 182 | bool |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 183 | default y if ARCH_X86 |
Stefan Reinauer | 8aedcbc | 2010-12-16 23:37:17 +0000 | [diff] [blame] | 184 | |
Lee Leahy | fdc8c8b | 2016-06-07 08:45:17 -0700 | [diff] [blame] | 185 | config BOOTBLOCK_DEBUG_SPINLOOP |
| 186 | bool |
| 187 | default n |
| 188 | help |
| 189 | Add a spin (JMP .) in bootblock_crt0.S during early bootblock to wait |
| 190 | for a JTAG debugger to break into the execution sequence. |
| 191 | |
Patrick Georgi | a865b17 | 2011-01-14 07:40:24 +0000 | [diff] [blame] | 192 | config HAVE_CMOS_DEFAULT |
| 193 | def_bool n |
Martin Roth | f76303e | 2016-11-16 15:45:22 -0700 | [diff] [blame] | 194 | depends on HAVE_OPTION_TABLE |
Patrick Georgi | a865b17 | 2011-01-14 07:40:24 +0000 | [diff] [blame] | 195 | |
| 196 | config CMOS_DEFAULT_FILE |
| 197 | string |
Patrick Georgi | b8fba86 | 2020-06-17 21:06:53 +0200 | [diff] [blame] | 198 | default "src/mainboard/\$(MAINBOARDDIR)/cmos.default" |
Patrick Georgi | a865b17 | 2011-01-14 07:40:24 +0000 | [diff] [blame] | 199 | depends on HAVE_CMOS_DEFAULT |
| 200 | |
Felix Held | 4e03727 | 2022-02-23 16:35:58 +0100 | [diff] [blame] | 201 | config HPET_MIN_TICKS |
| 202 | hex |
| 203 | |
Aaron Durbin | 65ac3d8 | 2016-02-11 14:36:19 -0600 | [diff] [blame] | 204 | config C_ENV_BOOTBLOCK_SIZE |
| 205 | hex |
Kyösti Mälkki | e76ce87 | 2020-05-25 08:52:07 +0300 | [diff] [blame] | 206 | default 0x40000 if !FIXED_BOOTBLOCK_SIZE |
| 207 | help |
| 208 | This is only the default maximum of bootblock size for linking |
| 209 | purposes. Platforms may provide different limit and need to |
| 210 | specify this when FIXED_BOOTBLOCK_SIZE is selected. |
Andrey Petrov | ccd300b | 2016-02-28 22:04:51 -0800 | [diff] [blame] | 211 | |
Kyösti Mälkki | 49dbbe9 | 2019-12-21 10:17:56 +0200 | [diff] [blame] | 212 | config FIXED_BOOTBLOCK_SIZE |
| 213 | bool |
| 214 | |
Andrey Petrov | ccd300b | 2016-02-28 22:04:51 -0800 | [diff] [blame] | 215 | # Default address romstage is to be linked at |
| 216 | config ROMSTAGE_ADDR |
| 217 | hex |
| 218 | default 0x2000000 |
| 219 | |
| 220 | # Default address verstage is to be linked at |
| 221 | config VERSTAGE_ADDR |
| 222 | hex |
| 223 | default 0x2000000 |
Aaron Durbin | 7f8afe0 | 2016-03-18 12:21:23 -0500 | [diff] [blame] | 224 | |
| 225 | # Use the post CAR infrastructure for tearing down cache-as-ram |
Elyes HAOUAS | 777ea89 | 2016-07-29 07:40:41 +0200 | [diff] [blame] | 226 | # from a program loaded in RAM and subsequently loading ramstage. |
Aaron Durbin | 7f8afe0 | 2016-03-18 12:21:23 -0500 | [diff] [blame] | 227 | config POSTCAR_STAGE |
Kyösti Mälkki | 0f5e01a | 2019-08-09 07:11:07 +0300 | [diff] [blame] | 228 | def_bool y |
| 229 | depends on ARCH_X86 |
Felix Held | ca928c6 | 2020-04-04 01:47:37 +0200 | [diff] [blame] | 230 | depends on !RESET_VECTOR_IN_RAM |
Lee Leahy | d131ea3 | 2016-06-08 13:40:08 -0700 | [diff] [blame] | 231 | |
| 232 | config VERSTAGE_DEBUG_SPINLOOP |
| 233 | bool |
| 234 | default n |
| 235 | help |
| 236 | Add a spin (JMP .) in assembly_entry.S during early verstage to wait |
| 237 | for a JTAG debugger to break into the execution sequence. |
| 238 | |
| 239 | config ROMSTAGE_DEBUG_SPINLOOP |
| 240 | bool |
| 241 | default n |
| 242 | help |
| 243 | Add a spin (JMP .) in assembly_entry.S during early romstage to wait |
| 244 | for a JTAG debugger to break into the execution sequence. |
Martin Roth | 408fda7 | 2016-12-15 16:04:55 -0700 | [diff] [blame] | 245 | |
| 246 | choice |
| 247 | prompt "Bootblock behaviour" |
| 248 | default BOOTBLOCK_SIMPLE |
Kyösti Mälkki | b8d575c | 2019-12-16 16:00:49 +0200 | [diff] [blame] | 249 | depends on !VBOOT |
Martin Roth | 408fda7 | 2016-12-15 16:04:55 -0700 | [diff] [blame] | 250 | |
| 251 | config BOOTBLOCK_SIMPLE |
| 252 | bool "Always load fallback" |
| 253 | |
| 254 | config BOOTBLOCK_NORMAL |
| 255 | bool "Switch to normal if CMOS says so" |
Arthur Heymans | 9bbfafb | 2024-02-18 14:02:35 +0100 | [diff] [blame] | 256 | select CONFIGURABLE_CBFS_PREFIX |
| 257 | select SEPARATE_ROMSTAGE |
Martin Roth | 408fda7 | 2016-12-15 16:04:55 -0700 | [diff] [blame] | 258 | |
| 259 | endchoice |
| 260 | |
Martin Roth | 408fda7 | 2016-12-15 16:04:55 -0700 | [diff] [blame] | 261 | config SKIP_MAX_REBOOT_CNT_CLEAR |
| 262 | bool "Do not clear reboot count after successful boot" |
| 263 | depends on BOOTBLOCK_NORMAL |
| 264 | help |
| 265 | Do not clear the reboot count immediately after successful boot. |
| 266 | Set to allow the payload to control normal/fallback image recovery. |
| 267 | Note that it is the responsibility of the payload to reset the |
Paul Menzel | b949902 | 2019-01-08 16:21:31 +0100 | [diff] [blame] | 268 | normal boot bit to 1 after each successful boot. |
Marc Jones | 7a2d4ea | 2017-08-25 18:54:23 -0600 | [diff] [blame] | 269 | |
Furquan Shaikh | bf4b7b0 | 2020-04-30 18:08:16 -0700 | [diff] [blame] | 270 | config ACPI_BERT |
Nico Huber | 9df72e0 | 2018-11-24 18:25:50 +0100 | [diff] [blame] | 271 | bool |
Marc Jones | 7a2d4ea | 2017-08-25 18:54:23 -0600 | [diff] [blame] | 272 | depends on HAVE_ACPI_TABLES |
| 273 | help |
Furquan Shaikh | bf4b7b0 | 2020-04-30 18:08:16 -0700 | [diff] [blame] | 274 | Build an ACPI Boot Error Record Table. |
Aaron Durbin | f49ddb6 | 2018-01-24 17:35:58 -0700 | [diff] [blame] | 275 | |
| 276 | config COLLECT_TIMESTAMPS_NO_TSC |
| 277 | bool |
| 278 | default n |
| 279 | depends on COLLECT_TIMESTAMPS |
| 280 | help |
| 281 | Use a non-TSC platform-dependent source for timestamps. |
| 282 | |
| 283 | config COLLECT_TIMESTAMPS_TSC |
| 284 | bool |
| 285 | default y if !COLLECT_TIMESTAMPS_NO_TSC |
| 286 | default n |
| 287 | depends on COLLECT_TIMESTAMPS |
| 288 | help |
| 289 | Use the TSC as the timestamp source. |
Aaron Durbin | 0f35af8f | 2018-04-18 01:00:27 -0600 | [diff] [blame] | 290 | |
| 291 | config PAGING_IN_CACHE_AS_RAM |
| 292 | bool |
| 293 | default n |
| 294 | depends on ARCH_X86 |
| 295 | help |
| 296 | Chipsets scan select this option to preallocate area in cache-as-ram |
| 297 | for storing paging data structures. PAE paging is currently the |
| 298 | only thing being supported. |
| 299 | |
| 300 | config NUM_CAR_PAGE_TABLE_PAGES |
| 301 | int |
| 302 | default 5 |
| 303 | depends on PAGING_IN_CACHE_AS_RAM |
| 304 | help |
| 305 | The number of 4KiB pages that should be pre-allocated for page tables. |
Aaron Durbin | 4b032e4 | 2018-04-20 01:39:30 -0600 | [diff] [blame] | 306 | |
| 307 | # Provide the interrupt handlers to every stage. Not all |
| 308 | # stages may take advantage. |
| 309 | config IDT_IN_EVERY_STAGE |
| 310 | bool |
| 311 | default n |
| 312 | depends on ARCH_X86 |
Nico Huber | 33fcaf9 | 2018-10-10 22:44:20 +0200 | [diff] [blame] | 313 | |
| 314 | config HAVE_CF9_RESET |
| 315 | bool |
| 316 | |
| 317 | config HAVE_CF9_RESET_PREPARE |
| 318 | bool |
| 319 | depends on HAVE_CF9_RESET |
Kyösti Mälkki | b72b5d9 | 2019-07-04 21:08:17 +0300 | [diff] [blame] | 320 | |
Felix Held | 6759ad3 | 2023-12-14 20:49:59 +0100 | [diff] [blame] | 321 | config HAVE_CONFIGURABLE_APMC_SMI_PORT |
| 322 | bool |
| 323 | help |
| 324 | SoCs that have a configurable APMC SMI command port, should select |
| 325 | this option and implement pm_acpi_smi_cmd_port() that returns the IO |
| 326 | port. |
| 327 | |
Kyösti Mälkki | b72b5d9 | 2019-07-04 21:08:17 +0300 | [diff] [blame] | 328 | config PIRQ_ROUTE |
| 329 | bool |
| 330 | default n |
| 331 | |
| 332 | config MAX_PIRQ_LINKS |
| 333 | int |
| 334 | default 4 |
| 335 | depends on PIRQ_ROUTE |
| 336 | help |
| 337 | This variable specifies the number of PIRQ interrupt links which are |
| 338 | routable. On most chipsets, this is 4, INTA through INTD. Some |
| 339 | chipsets offer more than four links, commonly up to INTH. They may |
| 340 | also have a separate link for ATA or IOAPIC interrupts. When the PIRQ |
| 341 | table specifies links greater than 4, pirq_route_irqs will not |
| 342 | function properly, unless this variable is correctly set. |
Arthur Heymans | b86e96a | 2019-02-10 17:00:56 +0100 | [diff] [blame] | 343 | |
Furquan Shaikh | 46514c2 | 2020-06-11 11:59:07 -0700 | [diff] [blame] | 344 | config MEMLAYOUT_LD_FILE |
| 345 | string |
| 346 | default "src/arch/x86/memlayout.ld" |
| 347 | |
Robert Zieba | 3f01cd1 | 2022-04-14 10:36:15 -0600 | [diff] [blame] | 348 | config DEBUG_HW_BREAKPOINTS |
| 349 | bool |
| 350 | default y |
| 351 | help |
| 352 | Enable support for hardware data and instruction breakpoints through |
| 353 | the x86 debug registers |
| 354 | |
| 355 | config DEBUG_HW_BREAKPOINTS_IN_ALL_STAGES |
| 356 | bool |
| 357 | default y |
| 358 | depends on DEBUG_HW_BREAKPOINTS && IDT_IN_EVERY_STAGE |
| 359 | |
| 360 | config DEBUG_NULL_DEREF_BREAKPOINTS |
| 361 | bool |
| 362 | default y |
| 363 | depends on DEBUG_HW_BREAKPOINTS |
| 364 | help |
| 365 | Enable support for catching null dereferences and instruction execution |
| 366 | |
| 367 | config DEBUG_NULL_DEREF_BREAKPOINTS_IN_ALL_STAGES |
| 368 | bool |
| 369 | default y |
| 370 | depends on DEBUG_NULL_DEREF_BREAKPOINTS && DEBUG_HW_BREAKPOINTS_IN_ALL_STAGES |
| 371 | |
| 372 | config DEBUG_NULL_DEREF_HALT |
| 373 | bool |
| 374 | default n |
| 375 | depends on DEBUG_NULL_DEREF_BREAKPOINTS |
| 376 | help |
| 377 | When enabled null dereferences and instruction fetches will halt execution. |
| 378 | Otherwise an error will be printed. |
| 379 | |
Bill XIE | f0215b4 | 2021-03-20 21:06:11 +0800 | [diff] [blame] | 380 | # Some EC need an "EC firmware pointer" (a data structure hinting the address |
| 381 | # of its firmware blobs) being put at a fixed position. Its space |
| 382 | # (__section__(".ecfw_ptr")) should be reserved if it lies in the range of a |
| 383 | # stage. Different EC may have different format and/or value for it. The actual |
| 384 | # address of EC firmware pointer should be provided in the Kconfig of the EC |
| 385 | # requiring it, and its value could be filled by linking a read-only global |
| 386 | # data object to the section above. |
| 387 | |
| 388 | config ECFW_PTR_ADDR |
| 389 | hex |
| 390 | help |
| 391 | Address of reserved space for EC firmware pointer, which should not |
| 392 | overlap other data such as reset vector or FIT pointer if present. |
| 393 | |
| 394 | config ECFW_PTR_SIZE |
| 395 | int |
| 396 | help |
| 397 | Size of reserved space for EC firmware pointer |
| 398 | |
Eric Lai | c1ef4f3 | 2023-06-12 14:27:54 +0800 | [diff] [blame] | 399 | config DUMP_SMBIOS_TYPE17 |
Eric Lai | 8bbe850 | 2023-06-26 07:56:39 +0800 | [diff] [blame] | 400 | bool "Dump part of SMBIOS type17 dimm information" |
Eric Lai | c1ef4f3 | 2023-06-12 14:27:54 +0800 | [diff] [blame] | 401 | depends on GENERATE_SMBIOS_TABLES |
| 402 | |
Jeremy Compostella | ba757a7 | 2023-12-20 09:07:04 -0800 | [diff] [blame] | 403 | config SOC_PHYSICAL_ADDRESS_WIDTH |
| 404 | int |
| 405 | default 0 |
| 406 | help |
| 407 | On some System-on-Chip the physical address size available |
| 408 | at the SoC level may be different than at the CPU |
| 409 | level. This configuration can be use to set the physical |
| 410 | address width (in bits) of the SoC. |
| 411 | |
| 412 | If not set, both CPU and SoC physical address width are |
| 413 | assume to be the same. |
| 414 | |
Arthur Heymans | b86e96a | 2019-02-10 17:00:56 +0100 | [diff] [blame] | 415 | endif |