Angel Pons | 0612b27 | 2020-04-05 15:46:56 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Subrata Banik | 2153ea5 | 2017-11-22 15:38:19 +0530 | [diff] [blame] | 2 | |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 3 | #include <device/pci_ops.h> |
Subrata Banik | 2153ea5 | 2017-11-22 15:38:19 +0530 | [diff] [blame] | 4 | #include <console/console.h> |
Subrata Banik | 2153ea5 | 2017-11-22 15:38:19 +0530 | [diff] [blame] | 5 | #include <device/pci.h> |
| 6 | #include <device/pci_ids.h> |
Tim Wawrzynczak | 6c6eb65 | 2021-07-01 09:03:51 -0600 | [diff] [blame] | 7 | #include <intelblocks/acpi.h> |
Subrata Banik | 2153ea5 | 2017-11-22 15:38:19 +0530 | [diff] [blame] | 8 | #include <intelblocks/pmc.h> |
Subrata Banik | af27ac2 | 2022-02-18 00:44:15 +0530 | [diff] [blame] | 9 | #include <intelblocks/pmclib.h> |
Subrata Banik | 2153ea5 | 2017-11-22 15:38:19 +0530 | [diff] [blame] | 10 | #include <soc/pci_devs.h> |
Subrata Banik | b3671ec | 2022-02-06 18:21:50 +0530 | [diff] [blame] | 11 | #include <soc/pm.h> |
Subrata Banik | 2153ea5 | 2017-11-22 15:38:19 +0530 | [diff] [blame] | 12 | |
Subrata Banik | 2153ea5 | 2017-11-22 15:38:19 +0530 | [diff] [blame] | 13 | static void pch_pmc_add_new_resource(struct device *dev, |
| 14 | uint8_t offset, uintptr_t base, size_t size, |
| 15 | unsigned long flags) |
| 16 | { |
| 17 | struct resource *res; |
| 18 | res = new_resource(dev, offset); |
| 19 | res->base = base; |
| 20 | res->size = size; |
| 21 | res->flags = flags; |
| 22 | } |
| 23 | |
| 24 | static void pch_pmc_add_mmio_resources(struct device *dev, |
| 25 | const struct pmc_resource_config *cfg) |
| 26 | { |
| 27 | pch_pmc_add_new_resource(dev, cfg->pwrmbase_offset, |
| 28 | cfg->pwrmbase_addr, cfg->pwrmbase_size, |
| 29 | IORESOURCE_MEM | IORESOURCE_ASSIGNED | |
| 30 | IORESOURCE_FIXED | IORESOURCE_RESERVE); |
| 31 | } |
| 32 | |
| 33 | static void pch_pmc_add_io_resources(struct device *dev, |
| 34 | const struct pmc_resource_config *cfg) |
| 35 | { |
| 36 | pch_pmc_add_new_resource(dev, cfg->abase_offset, |
| 37 | cfg->abase_addr, cfg->abase_size, |
| 38 | IORESOURCE_IO | IORESOURCE_ASSIGNED | |
| 39 | IORESOURCE_FIXED); |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 40 | if (CONFIG(PMC_INVALID_READ_AFTER_WRITE)) { |
Hannah Williams | 1177bf5 | 2017-12-13 12:44:26 -0800 | [diff] [blame] | 41 | /* |
| 42 | * The ACPI IO BAR (offset 0x20) is not PCI compliant. We've |
| 43 | * observed cases where the BAR reads back as 0, but the IO |
| 44 | * window is open. This also means that it will not respond |
| 45 | * to PCI probing. |
| 46 | */ |
| 47 | pci_write_config16(dev, cfg->abase_offset, cfg->abase_addr); |
| 48 | /* |
| 49 | * In pci_dev_enable_resources, reading IO SPACE ACCESS bit in |
| 50 | * STATUSCOMMAND register does not read back the written |
| 51 | * value correctly, hence IO access gets disabled. This is |
| 52 | * seen in some PMC devices, hence this code makes sure |
| 53 | * IO access is available. |
| 54 | */ |
| 55 | dev->command |= PCI_COMMAND_IO; |
| 56 | } |
Subrata Banik | 2153ea5 | 2017-11-22 15:38:19 +0530 | [diff] [blame] | 57 | } |
| 58 | |
| 59 | static void pch_pmc_read_resources(struct device *dev) |
| 60 | { |
| 61 | struct pmc_resource_config pmc_cfg; |
| 62 | struct pmc_resource_config *config = &pmc_cfg; |
| 63 | |
| 64 | if (pmc_soc_get_resources(config) < 0) |
lilacious | 40cb3fe | 2023-06-21 23:24:14 +0200 | [diff] [blame] | 65 | die_with_post_code(POSTCODE_HW_INIT_FAILURE, |
Keith Short | 15588b0 | 2019-05-09 11:40:34 -0600 | [diff] [blame] | 66 | "Unable to get PMC controller resource information!"); |
Subrata Banik | 2153ea5 | 2017-11-22 15:38:19 +0530 | [diff] [blame] | 67 | |
| 68 | /* Get the normal PCI resources of this device. */ |
| 69 | pci_dev_read_resources(dev); |
| 70 | |
| 71 | /* Add non-standard MMIO resources. */ |
| 72 | pch_pmc_add_mmio_resources(dev, config); |
| 73 | |
| 74 | /* Add IO resources. */ |
| 75 | pch_pmc_add_io_resources(dev, config); |
| 76 | } |
| 77 | |
Tim Wawrzynczak | 6c6eb65 | 2021-07-01 09:03:51 -0600 | [diff] [blame] | 78 | static void pmc_fill_ssdt(const struct device *dev) |
| 79 | { |
| 80 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP)) |
| 81 | generate_acpi_power_engine(); |
| 82 | } |
| 83 | |
Subrata Banik | b3671ec | 2022-02-06 18:21:50 +0530 | [diff] [blame] | 84 | /* |
| 85 | * `pmc_final` function is native implementation of equivalent events performed by |
| 86 | * each FSP NotifyPhase() API invocations. |
| 87 | * |
| 88 | * |
| 89 | * Clear PMCON status bits (Global Reset/Power Failure/Host Reset Status bits) |
| 90 | * |
| 91 | * Perform the PMCON status bit clear operation from `.final` |
| 92 | * to cover any such chances where later boot stage requested a global |
| 93 | * reset and PMCON status bit remains set. |
| 94 | */ |
| 95 | static void pmc_final(struct device *dev) |
| 96 | { |
| 97 | pmc_clear_pmcon_sts(); |
| 98 | } |
| 99 | |
Nico Huber | 5768619 | 2022-08-06 19:11:55 +0200 | [diff] [blame] | 100 | struct device_operations pmc_ops = { |
Elyes HAOUAS | 1d19127 | 2018-11-27 12:23:48 +0100 | [diff] [blame] | 101 | .read_resources = pch_pmc_read_resources, |
| 102 | .set_resources = pci_dev_set_resources, |
| 103 | .enable_resources = pci_dev_enable_resources, |
| 104 | .init = pmc_soc_init, |
Subrata Banik | 6bbc91a | 2017-12-07 14:55:51 +0530 | [diff] [blame] | 105 | .ops_pci = &pci_dev_ops_pci, |
Nico Huber | 51b75ae | 2019-03-14 16:02:05 +0100 | [diff] [blame] | 106 | .scan_bus = scan_static_bus, |
Tim Wawrzynczak | 6c6eb65 | 2021-07-01 09:03:51 -0600 | [diff] [blame] | 107 | #if CONFIG(HAVE_ACPI_TABLES) |
| 108 | .acpi_fill_ssdt = pmc_fill_ssdt, |
| 109 | #endif |
Subrata Banik | b3671ec | 2022-02-06 18:21:50 +0530 | [diff] [blame] | 110 | .final = pmc_final, |
Subrata Banik | 2153ea5 | 2017-11-22 15:38:19 +0530 | [diff] [blame] | 111 | }; |
| 112 | |
| 113 | static const unsigned short pci_device_ids[] = { |
Appukuttan V K | 50c8f2e | 2024-01-11 18:05:11 +0530 | [diff] [blame^] | 114 | PCI_DID_INTEL_LNL_PMC, |
Wonkyu Kim | 9f40107 | 2020-11-13 15:16:32 -0800 | [diff] [blame] | 115 | PCI_DID_INTEL_MTL_SOC_PMC, |
| 116 | PCI_DID_INTEL_MTL_IOE_M_PMC, |
| 117 | PCI_DID_INTEL_MTL_IOE_P_PMC, |
Bora Guvendik | a15b25f | 2022-02-28 14:43:49 -0800 | [diff] [blame] | 118 | PCI_DID_INTEL_RPP_P_PMC, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 119 | PCI_DID_INTEL_DNV_PMC, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 120 | PCI_DID_INTEL_LWB_PMC, |
| 121 | PCI_DID_INTEL_LWB_PMC_SUPER, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 122 | PCI_DID_INTEL_APL_PMC, |
| 123 | PCI_DID_INTEL_GLK_PMC, |
| 124 | PCI_DID_INTEL_CNP_H_PMC, |
| 125 | PCI_DID_INTEL_ICP_PMC, |
| 126 | PCI_DID_INTEL_CMP_PMC, |
| 127 | PCI_DID_INTEL_CMP_H_PMC, |
| 128 | PCI_DID_INTEL_TGP_PMC, |
| 129 | PCI_DID_INTEL_TGP_H_PMC, |
| 130 | PCI_DID_INTEL_MCC_PMC, |
| 131 | PCI_DID_INTEL_JSP_PMC, |
| 132 | PCI_DID_INTEL_ADP_P_PMC, |
| 133 | PCI_DID_INTEL_ADP_S_PMC, |
| 134 | PCI_DID_INTEL_ADP_M_N_PMC, |
Michał Żygowski | 24fba11 | 2023-08-25 12:20:17 +0200 | [diff] [blame] | 135 | PCI_DID_INTEL_RPP_S_PMC, |
Subrata Banik | 2153ea5 | 2017-11-22 15:38:19 +0530 | [diff] [blame] | 136 | 0 |
| 137 | }; |
| 138 | |
Subrata Banik | 8885206 | 2018-01-10 10:51:50 +0530 | [diff] [blame] | 139 | static const struct pci_driver pch_pmc __pci_driver = { |
Nico Huber | 5768619 | 2022-08-06 19:11:55 +0200 | [diff] [blame] | 140 | .ops = &pmc_ops, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 141 | .vendor = PCI_VID_INTEL, |
Subrata Banik | 2153ea5 | 2017-11-22 15:38:19 +0530 | [diff] [blame] | 142 | .devices = pci_device_ids, |
| 143 | }; |