Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
Arthur Heymans | fa5d0f8 | 2019-11-12 19:11:50 +0100 | [diff] [blame] | 17 | #include <bootblock_common.h> |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 18 | #include <stdint.h> |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 19 | #include <cpu/x86/lapic.h> |
| 20 | #include <pc80/mc146818rtc.h> |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 21 | #include <console/console.h> |
Kyösti Mälkki | e3ddee0 | 2014-05-03 10:45:28 +0300 | [diff] [blame] | 22 | #include <bootmode.h> |
Edward O'Callaghan | 1b3acb1 | 2014-06-01 18:04:05 +1000 | [diff] [blame] | 23 | #include <superio/ite/common/ite.h> |
| 24 | #include <superio/ite/it8772f/it8772f.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 25 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 26 | #include <northbridge/intel/sandybridge/raminit.h> |
Vladimir Serbinenko | d2990c9 | 2016-02-10 02:52:42 +0100 | [diff] [blame] | 27 | #include <northbridge/intel/sandybridge/raminit_native.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 28 | #include <southbridge/intel/bd82x6x/pch.h> |
Patrick Rudolph | e8e66f4 | 2016-02-06 17:42:42 +0100 | [diff] [blame] | 29 | #include <southbridge/intel/common/gpio.h> |
Edward O'Callaghan | 74834e0 | 2015-01-04 04:17:35 +1100 | [diff] [blame] | 30 | #include <superio/smsc/lpc47n207/lpc47n207.h> |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 31 | |
| 32 | /* Stumpy USB Reset Disable defined in cmos.layout */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 33 | #if CONFIG(USE_OPTION_TABLE) |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 34 | #include "option_table.h" |
| 35 | #define CMOS_USB_RESET_DISABLE (CMOS_VSTART_stumpy_usb_reset_disable >> 3) |
| 36 | #else |
| 37 | #define CMOS_USB_RESET_DISABLE (400 >> 3) |
| 38 | #endif |
| 39 | #define USB_RESET_DISABLE_MAGIC (0xdd) /* Disable if set to this */ |
| 40 | |
Elyes HAOUAS | f5f1b38 | 2018-04-26 09:43:03 +0200 | [diff] [blame] | 41 | #define SUPERIO_DEV PNP_DEV(0x2e, 0) |
Edward O'Callaghan | 1b3acb1 | 2014-06-01 18:04:05 +1000 | [diff] [blame] | 42 | #define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1) |
| 43 | #define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) |
| 44 | |
Arthur Heymans | 9c53834 | 2019-11-12 16:42:33 +0100 | [diff] [blame] | 45 | void mainboard_late_rcba_config(void) |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 46 | { |
Kyösti Mälkki | 6f49906 | 2015-06-06 11:52:24 +0300 | [diff] [blame] | 47 | /* |
| 48 | * GFX INTA -> PIRQA (MSI) |
| 49 | * D28IP_P1IP WLAN INTA -> PIRQB |
| 50 | * D28IP_P4IP ETH0 INTB -> PIRQC |
| 51 | * D29IP_E1P EHCI1 INTA -> PIRQD |
| 52 | * D26IP_E2P EHCI2 INTA -> PIRQE |
| 53 | * D31IP_SIP SATA INTA -> PIRQF (MSI) |
| 54 | * D31IP_SMIP SMBUS INTB -> PIRQG |
| 55 | * D31IP_TTIP THRT INTC -> PIRQH |
| 56 | * D27IP_ZIP HDA INTA -> PIRQG (MSI) |
| 57 | */ |
| 58 | |
| 59 | /* Device interrupt pin register (board specific) */ |
| 60 | RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | |
| 61 | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); |
| 62 | RCBA32(D30IP) = (NOINT << D30IP_PIP); |
| 63 | RCBA32(D29IP) = (INTA << D29IP_E1P); |
| 64 | RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | |
| 65 | (INTB << D28IP_P4IP); |
| 66 | RCBA32(D27IP) = (INTA << D27IP_ZIP); |
| 67 | RCBA32(D26IP) = (INTA << D26IP_E2P); |
| 68 | RCBA32(D25IP) = (NOINT << D25IP_LIP); |
| 69 | RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); |
| 70 | |
| 71 | /* Device interrupt route registers */ |
| 72 | DIR_ROUTE(D31IR, PIRQF, PIRQG, PIRQH, PIRQA); |
| 73 | DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); |
| 74 | DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); |
| 75 | DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB); |
| 76 | DIR_ROUTE(D26IR, PIRQE, PIRQF, PIRQG, PIRQH); |
| 77 | DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 78 | DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 79 | } |
| 80 | |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 81 | static void setup_sio_gpios(void) |
| 82 | { |
| 83 | /* |
| 84 | * GPIO10 as USBPWRON12# |
| 85 | * GPIO12 as USBPWRON13# |
| 86 | */ |
Elyes HAOUAS | f5f1b38 | 2018-04-26 09:43:03 +0200 | [diff] [blame] | 87 | it8772f_gpio_setup(SUPERIO_DEV, 1, 0x05, 0x05, 0x00, 0x05, 0x05); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 88 | |
| 89 | /* |
| 90 | * GPIO22 as wake SCI# |
| 91 | */ |
Elyes HAOUAS | f5f1b38 | 2018-04-26 09:43:03 +0200 | [diff] [blame] | 92 | it8772f_gpio_setup(SUPERIO_DEV, 2, 0x04, 0x04, 0x00, 0x04, 0x04); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 93 | |
| 94 | /* |
| 95 | * GPIO32 as EXTSMI# |
| 96 | */ |
Elyes HAOUAS | f5f1b38 | 2018-04-26 09:43:03 +0200 | [diff] [blame] | 97 | it8772f_gpio_setup(SUPERIO_DEV, 3, 0x04, 0x04, 0x00, 0x04, 0x04); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 98 | |
| 99 | /* |
| 100 | * GPIO45 as LED_POWER# |
| 101 | */ |
Matt DeVillier | ffae746 | 2016-11-07 16:43:03 -0600 | [diff] [blame] | 102 | it8772f_gpio_led(GPIO_DEV, 4 /* set */, (0x1 << 5) /* select */, |
| 103 | (0x1 << 5) /* polarity */, (0x1 << 5) /* 1 = pullup */, |
Elyes HAOUAS | a5aad2e | 2016-09-19 09:47:16 -0600 | [diff] [blame] | 104 | (0x1 << 5) /* output */, (0x1 << 5) /* 1 = Simple IO function */, |
david | 80ef7b7 | 2015-01-19 17:11:36 +0800 | [diff] [blame] | 105 | SIO_GPIO_BLINK_GPIO45, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 106 | |
| 107 | /* |
| 108 | * GPIO51 as USBPWRON8# |
| 109 | * GPIO52 as USBPWRON1# |
| 110 | */ |
Elyes HAOUAS | f5f1b38 | 2018-04-26 09:43:03 +0200 | [diff] [blame] | 111 | it8772f_gpio_setup(SUPERIO_DEV, 5, 0x06, 0x06, 0x00, 0x06, 0x06); |
| 112 | it8772f_gpio_setup(SUPERIO_DEV, 6, 0x00, 0x00, 0x00, 0x00, 0x00); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 113 | } |
| 114 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 115 | void mainboard_fill_pei_data(struct pei_data *pei_data) |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 116 | { |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 117 | struct pei_data pei_data_template = { |
Edward O'Callaghan | b27d360 | 2014-05-24 02:40:31 +1000 | [diff] [blame] | 118 | .pei_version = PEI_VERSION, |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 119 | .mchbar = (uintptr_t)DEFAULT_MCHBAR, |
| 120 | .dmibar = (uintptr_t)DEFAULT_DMIBAR, |
Edward O'Callaghan | b27d360 | 2014-05-24 02:40:31 +1000 | [diff] [blame] | 121 | .epbar = DEFAULT_EPBAR, |
| 122 | .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, |
| 123 | .smbusbar = SMBUS_IO_BASE, |
| 124 | .wdbbar = 0x4000000, |
| 125 | .wdbsize = 0x1000, |
| 126 | .hpet_address = CONFIG_HPET_ADDRESS, |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 127 | .rcba = (uintptr_t)DEFAULT_RCBABASE, |
Edward O'Callaghan | b27d360 | 2014-05-24 02:40:31 +1000 | [diff] [blame] | 128 | .pmbase = DEFAULT_PMBASE, |
| 129 | .gpiobase = DEFAULT_GPIOBASE, |
| 130 | .thermalbase = 0xfed08000, |
| 131 | .system_type = 0, // 0 Mobile, 1 Desktop/Server |
| 132 | .tseg_size = CONFIG_SMM_TSEG_SIZE, |
| 133 | .spd_addresses = { 0xa0, 0x00,0xa4,0x00 }, |
| 134 | .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, |
| 135 | .ec_present = 0, |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 136 | // 0 = leave channel enabled |
| 137 | // 1 = disable dimm 0 on channel |
| 138 | // 2 = disable dimm 1 on channel |
| 139 | // 3 = disable dimm 0+1 on channel |
Edward O'Callaghan | b27d360 | 2014-05-24 02:40:31 +1000 | [diff] [blame] | 140 | .dimm_channel0_disabled = 2, |
| 141 | .dimm_channel1_disabled = 2, |
| 142 | .max_ddr3_freq = 1333, |
| 143 | .usb_port_config = { |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 144 | { 1, 0, 0x0080 }, /* P0: Front port (OC0) */ |
| 145 | { 1, 1, 0x0040 }, /* P1: Back port (OC1) */ |
| 146 | { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */ |
| 147 | { 1, 0, 0x0040 }, /* P3: MMC (no OC) */ |
| 148 | { 1, 2, 0x0080 }, /* P4: Front port (OC2) */ |
| 149 | { 0, 0, 0x0000 }, /* P5: Empty */ |
| 150 | { 0, 0, 0x0000 }, /* P6: Empty */ |
| 151 | { 0, 0, 0x0000 }, /* P7: Empty */ |
| 152 | { 1, 4, 0x0040 }, /* P8: Back port (OC4) */ |
| 153 | { 1, 4, 0x0040 }, /* P9: MINIPCIE3 (no OC) */ |
| 154 | { 1, 4, 0x0040 }, /* P10: BLUETOOTH (no OC) */ |
| 155 | { 0, 4, 0x0000 }, /* P11: Empty */ |
| 156 | { 1, 6, 0x0040 }, /* P12: Back port (OC6) */ |
| 157 | { 1, 5, 0x0040 }, /* P13: Back port (OC5) */ |
| 158 | }, |
| 159 | }; |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 160 | *pei_data = pei_data_template; |
| 161 | } |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 162 | |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 163 | void mainboard_get_spd(spd_raw_data *spd, bool id_only) |
Vladimir Serbinenko | d2990c9 | 2016-02-10 02:52:42 +0100 | [diff] [blame] | 164 | { |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 165 | read_spd(&spd[0], 0x50, id_only); |
| 166 | read_spd(&spd[2], 0x52, id_only); |
Vladimir Serbinenko | d2990c9 | 2016-02-10 02:52:42 +0100 | [diff] [blame] | 167 | } |
| 168 | |
| 169 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 170 | /* enabled power usb oc pin */ |
| 171 | { 1, 1, 0 }, /* P0: Front port (OC0) */ |
| 172 | { 1, 0, 1 }, /* P1: Back port (OC1) */ |
| 173 | { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ |
| 174 | { 1, 0, -1 }, /* P3: MMC (no OC) */ |
| 175 | { 1, 1, 2 }, /* P4: Front port (OC2) */ |
| 176 | { 0, 0, -1 }, /* P5: Empty */ |
| 177 | { 0, 0, -1 }, /* P6: Empty */ |
| 178 | { 0, 0, -1 }, /* P7: Empty */ |
| 179 | { 1, 0, 4 }, /* P8: Back port (OC4) */ |
| 180 | { 1, 0, -1 }, /* P9: MINIPCIE3 (no OC) */ |
| 181 | { 1, 0, -1 }, /* P10: BLUETOOTH (no OC) */ |
| 182 | { 0, 0, -1 }, /* P11: Empty */ |
| 183 | { 1, 0, 6 }, /* P12: Back port (OC6) */ |
| 184 | { 1, 0, 5 }, /* P13: Back port (OC5) */ |
| 185 | }; |
| 186 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 187 | void mainboard_early_init(int s3resume) |
| 188 | { |
Kyösti Mälkki | e3ddee0 | 2014-05-03 10:45:28 +0300 | [diff] [blame] | 189 | init_bootmode_straps(); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 190 | } |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 191 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 192 | int mainboard_should_reset_usb(int s3resume) |
| 193 | { |
| 194 | if (s3resume) { |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 195 | /* |
| 196 | * For Stumpy the back USB ports are reset on resume |
| 197 | * so default to resetting the controller to make the |
| 198 | * kernel happy. There is a CMOS flag to disable the |
| 199 | * controller reset in case the kernel can tolerate |
| 200 | * the device power loss better in the future. |
| 201 | */ |
| 202 | u8 magic = cmos_read(CMOS_USB_RESET_DISABLE); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 203 | if (magic == USB_RESET_DISABLE_MAGIC) { |
| 204 | printk(BIOS_DEBUG, "USB Controller Reset Disabled\n"); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 205 | return 0; |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 206 | } else { |
| 207 | printk(BIOS_DEBUG, "USB Controller Reset Enabled\n"); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 208 | return 1; |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 209 | } |
| 210 | } else { |
| 211 | /* Ensure USB reset on resume is enabled at boot */ |
| 212 | cmos_write(0, CMOS_USB_RESET_DISABLE); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 213 | return 1; |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 214 | } |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 215 | } |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 216 | |
Arthur Heymans | fa5d0f8 | 2019-11-12 19:11:50 +0100 | [diff] [blame] | 217 | void bootblock_mainboard_early_init(void) |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 218 | { |
Nico Huber | 25128a7 | 2019-11-17 01:24:44 +0100 | [diff] [blame] | 219 | if (CONFIG(DRIVERS_UART_8250IO)) |
| 220 | try_enabling_LPC47N207_uart(); |
| 221 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 222 | setup_sio_gpios(); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 223 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 224 | /* Early SuperIO setup */ |
Elyes HAOUAS | f5f1b38 | 2018-04-26 09:43:03 +0200 | [diff] [blame] | 225 | it8772f_ac_resume_southbridge(SUPERIO_DEV); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 226 | ite_kill_watchdog(GPIO_DEV); |
| 227 | ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 228 | } |