Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | /* |
| 4 | * This file is created based on Intel Alder Lake Processor CPU Datasheet |
| 5 | * Document number: 619501 |
| 6 | * Chapter number: 14 |
| 7 | */ |
| 8 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 9 | #include <console/console.h> |
| 10 | #include <device/pci.h> |
Tim Wawrzynczak | 6cf79d9 | 2021-07-30 10:37:55 -0600 | [diff] [blame] | 11 | #include <device/pci_ids.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 12 | #include <cpu/x86/mp.h> |
| 13 | #include <cpu/x86/msr.h> |
| 14 | #include <cpu/intel/smm_reloc.h> |
| 15 | #include <cpu/intel/turbo.h> |
Michael Niewöhner | 10ae1cf | 2020-10-11 14:05:32 +0200 | [diff] [blame] | 16 | #include <cpu/intel/common/common.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 17 | #include <fsp/api.h> |
| 18 | #include <intelblocks/cpulib.h> |
| 19 | #include <intelblocks/mp_init.h> |
| 20 | #include <intelblocks/msr.h> |
Sridhar Siricilla | 23e2cde | 2022-01-14 19:20:15 +0530 | [diff] [blame] | 21 | #include <intelblocks/acpi.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 22 | #include <soc/cpu.h> |
| 23 | #include <soc/msr.h> |
| 24 | #include <soc/pci_devs.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 25 | #include <soc/soc_chip.h> |
Felix Held | d27ef5b | 2021-10-20 20:18:12 +0200 | [diff] [blame] | 26 | #include <types.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 27 | |
Sridhar Siricilla | 23e2cde | 2022-01-14 19:20:15 +0530 | [diff] [blame] | 28 | enum alderlake_model { |
| 29 | ADL_MODEL_P_M = 0x9A, |
| 30 | ADL_MODEL_N = 0xBE, |
| 31 | }; |
| 32 | |
Subrata Banik | 56ab8e2 | 2022-01-07 13:40:19 +0000 | [diff] [blame] | 33 | bool cpu_soc_is_in_untrusted_mode(void) |
| 34 | { |
| 35 | msr_t msr; |
| 36 | |
| 37 | msr = rdmsr(MSR_BIOS_DONE); |
| 38 | return !!(msr.lo & ENABLE_IA_UNTRUSTED); |
| 39 | } |
| 40 | |
Subrata Banik | 37a55d1 | 2022-05-30 18:11:12 +0000 | [diff] [blame] | 41 | void cpu_soc_bios_done(void) |
| 42 | { |
| 43 | msr_t msr; |
| 44 | |
| 45 | msr = rdmsr(MSR_BIOS_DONE); |
| 46 | msr.lo |= ENABLE_IA_UNTRUSTED; |
| 47 | wrmsr(MSR_BIOS_DONE, msr); |
| 48 | } |
| 49 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 50 | static void soc_fsp_load(void) |
| 51 | { |
Kyösti Mälkki | cc93c6e | 2021-01-09 22:53:52 +0200 | [diff] [blame] | 52 | fsps_load(); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 53 | } |
| 54 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 55 | static void configure_misc(void) |
| 56 | { |
| 57 | msr_t msr; |
| 58 | |
Tim Wawrzynczak | b0d3a01 | 2021-12-02 16:19:29 -0700 | [diff] [blame] | 59 | const config_t *conf = config_of_soc(); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 60 | |
| 61 | msr = rdmsr(IA32_MISC_ENABLE); |
| 62 | msr.lo |= (1 << 0); /* Fast String enable */ |
| 63 | msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ |
| 64 | wrmsr(IA32_MISC_ENABLE, msr); |
| 65 | |
| 66 | /* Set EIST status */ |
| 67 | cpu_set_eist(conf->eist_enable); |
| 68 | |
| 69 | /* Disable Thermal interrupts */ |
| 70 | msr.lo = 0; |
| 71 | msr.hi = 0; |
| 72 | wrmsr(IA32_THERM_INTERRUPT, msr); |
| 73 | |
| 74 | /* Enable package critical interrupt only */ |
| 75 | msr.lo = 1 << 4; |
| 76 | msr.hi = 0; |
| 77 | wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); |
| 78 | |
Jeremy Compostella | 117770d | 2022-07-21 15:40:03 -0700 | [diff] [blame] | 79 | /* Enable PROCHOT and Energy/Performance Bias control */ |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 80 | msr = rdmsr(MSR_POWER_CTL); |
Angel Pons | 4d794bd | 2021-10-11 14:00:54 +0200 | [diff] [blame] | 81 | msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */ |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 82 | msr.lo |= (1 << 23); /* Lock it */ |
Jeremy Compostella | 117770d | 2022-07-21 15:40:03 -0700 | [diff] [blame] | 83 | msr.lo |= (1 << 18); /* Energy/Performance Bias control */ |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 84 | wrmsr(MSR_POWER_CTL, msr); |
| 85 | } |
| 86 | |
Sridhar Siricilla | 23e2cde | 2022-01-14 19:20:15 +0530 | [diff] [blame] | 87 | enum core_type get_soc_cpu_type(void) |
| 88 | { |
| 89 | struct cpuinfo_x86 cpuinfo; |
| 90 | |
| 91 | if (cpu_is_hybrid_supported()) |
| 92 | return cpu_get_cpu_type(); |
| 93 | |
| 94 | get_fms(&cpuinfo, cpuid_eax(1)); |
| 95 | |
| 96 | if (cpuinfo.x86 == 0x6 && cpuinfo.x86_model == ADL_MODEL_N) |
| 97 | return CPUID_CORE_TYPE_INTEL_ATOM; |
| 98 | else |
| 99 | return CPUID_CORE_TYPE_INTEL_CORE; |
| 100 | } |
| 101 | |
Sridahr Siricilla | 73b90c6 | 2021-11-11 01:10:16 +0530 | [diff] [blame] | 102 | bool soc_is_nominal_freq_supported(void) |
| 103 | { |
| 104 | return true; |
| 105 | } |
| 106 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 107 | /* All CPUs including BSP will run the following function. */ |
| 108 | void soc_core_init(struct device *cpu) |
| 109 | { |
| 110 | /* Clear out pending MCEs */ |
| 111 | /* TODO(adurbin): This should only be done on a cold boot. Also, some |
| 112 | * of these banks are core vs package scope. For now every CPU clears |
| 113 | * every bank. */ |
| 114 | mca_configure(); |
| 115 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 116 | enable_lapic_tpr(); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 117 | |
| 118 | /* Configure Enhanced SpeedStep and Thermal Sensors */ |
| 119 | configure_misc(); |
| 120 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 121 | enable_pm_timer_emulation(); |
| 122 | |
| 123 | /* Enable Direct Cache Access */ |
| 124 | configure_dca_cap(); |
| 125 | |
Sridhar Siricilla | 44c1b5e | 2023-03-30 10:13:18 +0530 | [diff] [blame] | 126 | /* Set core type in struct cpu_info */ |
| 127 | set_dev_core_type(); |
| 128 | |
Jeremy Compostella | cd6a2ad | 2022-07-21 14:08:08 -0700 | [diff] [blame] | 129 | /* Set energy policy. The "normal" EPB (6) is not suitable for Alder |
| 130 | * Lake or Raptor Lake CPUs, as this results in higher uncore power. */ |
| 131 | set_energy_perf_bias(7); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 132 | |
Cliff Huang | 0bb2225 | 2022-03-07 18:42:13 -0800 | [diff] [blame] | 133 | const config_t *conf = config_of_soc(); |
| 134 | /* Set energy-performance preference */ |
| 135 | if (conf->enable_energy_perf_pref) |
| 136 | if (check_energy_perf_cap()) |
| 137 | set_energy_perf_pref(conf->energy_perf_pref_value); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 138 | /* Enable Turbo */ |
| 139 | enable_turbo(); |
Subrata Banik | 069b6d0 | 2022-08-15 16:38:49 +0530 | [diff] [blame] | 140 | |
Subrata Banik | 766bd00 | 2022-08-23 19:29:07 +0530 | [diff] [blame] | 141 | if (CONFIG(INTEL_TME) && is_tme_supported()) |
Subrata Banik | 069b6d0 | 2022-08-15 16:38:49 +0530 | [diff] [blame] | 142 | set_tme_core_activate(); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 143 | } |
| 144 | |
| 145 | static void per_cpu_smm_trigger(void) |
| 146 | { |
| 147 | /* Relocate the SMM handler. */ |
| 148 | smm_relocate(); |
| 149 | } |
| 150 | |
Cliff Huang | 0bb2225 | 2022-03-07 18:42:13 -0800 | [diff] [blame] | 151 | static void pre_mp_init(void) |
| 152 | { |
| 153 | soc_fsp_load(); |
| 154 | |
| 155 | const config_t *conf = config_of_soc(); |
| 156 | if (conf->enable_energy_perf_pref) { |
| 157 | if (check_energy_perf_cap()) |
| 158 | enable_energy_perf_pref(); |
| 159 | else |
| 160 | printk(BIOS_WARNING, "Energy Performance Preference not supported!\n"); |
| 161 | } |
| 162 | } |
| 163 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 164 | static void post_mp_init(void) |
| 165 | { |
| 166 | /* Set Max Ratio */ |
| 167 | cpu_set_max_ratio(); |
| 168 | |
| 169 | /* |
Kane Chen | 3aee3ad | 2021-05-04 09:53:38 +0800 | [diff] [blame] | 170 | * 1. Now that all APs have been relocated as well as the BSP let SMIs |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 171 | * start flowing. |
Kane Chen | 3aee3ad | 2021-05-04 09:53:38 +0800 | [diff] [blame] | 172 | * 2. Skip enabling power button SMI and enable it after BS_CHIPS_INIT |
| 173 | * to avoid shutdown hang due to lack of init on certain IP in FSP-S. |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 174 | */ |
Kane Chen | 3aee3ad | 2021-05-04 09:53:38 +0800 | [diff] [blame] | 175 | global_smi_enable_no_pwrbtn(); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 176 | } |
| 177 | |
| 178 | static const struct mp_ops mp_ops = { |
| 179 | /* |
| 180 | * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP, |
| 181 | * that are set prior to ramstage. |
| 182 | * Real MTRRs programming are being done after resource allocation. |
| 183 | */ |
Cliff Huang | 0bb2225 | 2022-03-07 18:42:13 -0800 | [diff] [blame] | 184 | .pre_mp_init = pre_mp_init, |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 185 | .get_cpu_count = get_cpu_count, |
| 186 | .get_smm_info = smm_info, |
| 187 | .get_microcode_info = get_microcode_info, |
| 188 | .pre_mp_smm_init = smm_initialize, |
| 189 | .per_cpu_smm_trigger = per_cpu_smm_trigger, |
| 190 | .relocation_handler = smm_relocation_handler, |
| 191 | .post_mp_init = post_mp_init, |
| 192 | }; |
| 193 | |
Arthur Heymans | 829e8e6 | 2023-01-30 19:09:34 +0100 | [diff] [blame] | 194 | void mp_init_cpus(struct bus *cpu_bus) |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 195 | { |
Felix Held | 4dd7d11 | 2021-10-20 23:31:43 +0200 | [diff] [blame] | 196 | /* TODO: Handle mp_init_with_smm failure? */ |
| 197 | mp_init_with_smm(cpu_bus, &mp_ops); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 198 | |
| 199 | /* Thermal throttle activation offset */ |
| 200 | configure_tcc_thermal_target(); |
| 201 | } |
Tim Wawrzynczak | 6cf79d9 | 2021-07-30 10:37:55 -0600 | [diff] [blame] | 202 | |
| 203 | enum adl_cpu_type get_adl_cpu_type(void) |
| 204 | { |
| 205 | const uint16_t adl_m_mch_ids[] = { |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 206 | PCI_DID_INTEL_ADL_M_ID_1, |
| 207 | PCI_DID_INTEL_ADL_M_ID_2, |
Tim Wawrzynczak | 6cf79d9 | 2021-07-30 10:37:55 -0600 | [diff] [blame] | 208 | }; |
| 209 | const uint16_t adl_p_mch_ids[] = { |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 210 | PCI_DID_INTEL_ADL_P_ID_1, |
| 211 | PCI_DID_INTEL_ADL_P_ID_3, |
| 212 | PCI_DID_INTEL_ADL_P_ID_4, |
| 213 | PCI_DID_INTEL_ADL_P_ID_5, |
| 214 | PCI_DID_INTEL_ADL_P_ID_6, |
| 215 | PCI_DID_INTEL_ADL_P_ID_7, |
| 216 | PCI_DID_INTEL_ADL_P_ID_8, |
| 217 | PCI_DID_INTEL_ADL_P_ID_9, |
| 218 | PCI_DID_INTEL_ADL_P_ID_10 |
Tim Wawrzynczak | 6cf79d9 | 2021-07-30 10:37:55 -0600 | [diff] [blame] | 219 | }; |
| 220 | const uint16_t adl_s_mch_ids[] = { |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 221 | PCI_DID_INTEL_ADL_S_ID_1, |
| 222 | PCI_DID_INTEL_ADL_S_ID_2, |
| 223 | PCI_DID_INTEL_ADL_S_ID_3, |
| 224 | PCI_DID_INTEL_ADL_S_ID_4, |
| 225 | PCI_DID_INTEL_ADL_S_ID_5, |
| 226 | PCI_DID_INTEL_ADL_S_ID_6, |
| 227 | PCI_DID_INTEL_ADL_S_ID_7, |
| 228 | PCI_DID_INTEL_ADL_S_ID_8, |
| 229 | PCI_DID_INTEL_ADL_S_ID_9, |
| 230 | PCI_DID_INTEL_ADL_S_ID_10, |
| 231 | PCI_DID_INTEL_ADL_S_ID_11, |
| 232 | PCI_DID_INTEL_ADL_S_ID_12, |
| 233 | PCI_DID_INTEL_ADL_S_ID_13, |
| 234 | PCI_DID_INTEL_ADL_S_ID_14, |
| 235 | PCI_DID_INTEL_ADL_S_ID_15, |
Tim Wawrzynczak | 6cf79d9 | 2021-07-30 10:37:55 -0600 | [diff] [blame] | 236 | }; |
| 237 | |
Usha P | 93f50b3 | 2021-12-02 14:18:10 +0530 | [diff] [blame] | 238 | const uint16_t adl_n_mch_ids[] = { |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 239 | PCI_DID_INTEL_ADL_N_ID_1, |
| 240 | PCI_DID_INTEL_ADL_N_ID_2, |
| 241 | PCI_DID_INTEL_ADL_N_ID_3, |
| 242 | PCI_DID_INTEL_ADL_N_ID_4, |
Usha P | 93f50b3 | 2021-12-02 14:18:10 +0530 | [diff] [blame] | 243 | }; |
| 244 | |
Tim Crawford | 53c6eea | 2023-07-07 09:59:56 -0600 | [diff] [blame] | 245 | const uint16_t rpl_hx_mch_ids[] = { |
| 246 | PCI_DID_INTEL_RPL_HX_ID_1, |
| 247 | PCI_DID_INTEL_RPL_HX_ID_2, |
| 248 | PCI_DID_INTEL_RPL_HX_ID_3, |
| 249 | PCI_DID_INTEL_RPL_HX_ID_4, |
| 250 | PCI_DID_INTEL_RPL_HX_ID_5, |
| 251 | PCI_DID_INTEL_RPL_HX_ID_6, |
| 252 | PCI_DID_INTEL_RPL_HX_ID_7, |
| 253 | PCI_DID_INTEL_RPL_HX_ID_8, |
| 254 | }; |
| 255 | |
Max Fritz | 573e6de | 2022-11-19 01:54:44 +0100 | [diff] [blame] | 256 | const uint16_t rpl_s_mch_ids[] = { |
| 257 | PCI_DID_INTEL_RPL_S_ID_1, |
| 258 | PCI_DID_INTEL_RPL_S_ID_2, |
| 259 | PCI_DID_INTEL_RPL_S_ID_3, |
| 260 | PCI_DID_INTEL_RPL_S_ID_4, |
| 261 | PCI_DID_INTEL_RPL_S_ID_5 |
| 262 | }; |
| 263 | |
Bora Guvendik | a15b25f | 2022-02-28 14:43:49 -0800 | [diff] [blame] | 264 | const uint16_t rpl_p_mch_ids[] = { |
| 265 | PCI_DID_INTEL_RPL_P_ID_1, |
| 266 | PCI_DID_INTEL_RPL_P_ID_2, |
zhixingma | 529a64b | 2022-06-13 15:06:27 -0700 | [diff] [blame] | 267 | PCI_DID_INTEL_RPL_P_ID_3, |
Lawrence Chang | 0a5da51 | 2022-10-19 14:38:41 +0800 | [diff] [blame] | 268 | PCI_DID_INTEL_RPL_P_ID_4, |
Marx Wang | 39ede0a | 2022-12-20 10:48:33 +0800 | [diff] [blame] | 269 | PCI_DID_INTEL_RPL_P_ID_5, |
Bora Guvendik | a15b25f | 2022-02-28 14:43:49 -0800 | [diff] [blame] | 270 | }; |
| 271 | |
Tim Wawrzynczak | 6cf79d9 | 2021-07-30 10:37:55 -0600 | [diff] [blame] | 272 | const uint16_t mchid = pci_s_read_config16(PCI_DEV(0, PCI_SLOT(SA_DEVFN_ROOT), |
| 273 | PCI_FUNC(SA_DEVFN_ROOT)), |
| 274 | PCI_DEVICE_ID); |
| 275 | |
| 276 | for (size_t i = 0; i < ARRAY_SIZE(adl_p_mch_ids); i++) { |
| 277 | if (adl_p_mch_ids[i] == mchid) |
| 278 | return ADL_P; |
| 279 | } |
| 280 | |
| 281 | for (size_t i = 0; i < ARRAY_SIZE(adl_m_mch_ids); i++) { |
| 282 | if (adl_m_mch_ids[i] == mchid) |
| 283 | return ADL_M; |
| 284 | } |
| 285 | |
| 286 | for (size_t i = 0; i < ARRAY_SIZE(adl_s_mch_ids); i++) { |
| 287 | if (adl_s_mch_ids[i] == mchid) |
| 288 | return ADL_S; |
| 289 | } |
| 290 | |
Max Fritz | 573e6de | 2022-11-19 01:54:44 +0100 | [diff] [blame] | 291 | for (size_t i = 0; i < ARRAY_SIZE(rpl_s_mch_ids); i++) { |
| 292 | if (rpl_s_mch_ids[i] == mchid) |
| 293 | return RPL_S; |
| 294 | } |
| 295 | |
Usha P | 93f50b3 | 2021-12-02 14:18:10 +0530 | [diff] [blame] | 296 | for (size_t i = 0; i < ARRAY_SIZE(adl_n_mch_ids); i++) { |
| 297 | if (adl_n_mch_ids[i] == mchid) |
| 298 | return ADL_N; |
| 299 | } |
| 300 | |
Tim Crawford | 53c6eea | 2023-07-07 09:59:56 -0600 | [diff] [blame] | 301 | for (size_t i = 0; i < ARRAY_SIZE(rpl_hx_mch_ids); i++) { |
| 302 | if (rpl_hx_mch_ids[i] == mchid) |
| 303 | return RPL_HX; |
| 304 | } |
| 305 | |
Bora Guvendik | a15b25f | 2022-02-28 14:43:49 -0800 | [diff] [blame] | 306 | for (size_t i = 0; i < ARRAY_SIZE(rpl_p_mch_ids); i++) { |
| 307 | if (rpl_p_mch_ids[i] == mchid) |
| 308 | return RPL_P; |
| 309 | } |
| 310 | |
Tim Wawrzynczak | 6cf79d9 | 2021-07-30 10:37:55 -0600 | [diff] [blame] | 311 | return ADL_UNKNOWN; |
| 312 | } |
Tim Wawrzynczak | e2b8f30 | 2021-07-19 15:35:47 -0600 | [diff] [blame] | 313 | |
| 314 | uint8_t get_supported_lpm_mask(void) |
| 315 | { |
| 316 | enum adl_cpu_type type = get_adl_cpu_type(); |
| 317 | switch (type) { |
| 318 | case ADL_M: /* fallthrough */ |
Usha P | 93f50b3 | 2021-12-02 14:18:10 +0530 | [diff] [blame] | 319 | case ADL_N: |
Tim Wawrzynczak | e2b8f30 | 2021-07-19 15:35:47 -0600 | [diff] [blame] | 320 | case ADL_P: |
Bora Guvendik | a15b25f | 2022-02-28 14:43:49 -0800 | [diff] [blame] | 321 | case RPL_P: |
Tim Wawrzynczak | e2b8f30 | 2021-07-19 15:35:47 -0600 | [diff] [blame] | 322 | return LPM_S0i2_0 | LPM_S0i3_0; |
| 323 | case ADL_S: |
Max Fritz | 573e6de | 2022-11-19 01:54:44 +0100 | [diff] [blame] | 324 | case RPL_S: |
Tim Crawford | 53c6eea | 2023-07-07 09:59:56 -0600 | [diff] [blame] | 325 | case RPL_HX: |
Tim Wawrzynczak | e2b8f30 | 2021-07-19 15:35:47 -0600 | [diff] [blame] | 326 | return LPM_S0i2_0 | LPM_S0i2_1; |
| 327 | default: |
| 328 | printk(BIOS_ERR, "Unknown ADL CPU type: %d\n", type); |
| 329 | return 0; |
| 330 | } |
| 331 | } |