Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 2 | |
Arthur Heymans | 44807ac | 2022-09-13 12:43:37 +0200 | [diff] [blame^] | 3 | #include <amdblocks/cpu.h> |
Felix Held | 199b10f | 2022-08-13 00:29:23 +0200 | [diff] [blame] | 4 | #include <amdblocks/iomap.h> |
Felix Held | f1093af | 2021-07-13 23:00:26 +0200 | [diff] [blame] | 5 | #include <amdblocks/mca.h> |
Felix Held | a5cdf75 | 2021-03-10 15:47:00 +0100 | [diff] [blame] | 6 | #include <amdblocks/reset.h> |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 7 | #include <amdblocks/smm.h> |
Arthur Heymans | 615818f | 2022-05-31 21:33:43 +0200 | [diff] [blame] | 8 | #include <console/console.h> |
Felix Held | 285dd6e | 2021-02-17 22:16:40 +0100 | [diff] [blame] | 9 | #include <cpu/amd/msr.h> |
Arthur Heymans | 615818f | 2022-05-31 21:33:43 +0200 | [diff] [blame] | 10 | #include <cpu/amd/mtrr.h> |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 11 | #include <cpu/cpu.h> |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 12 | #include <cpu/x86/mp.h> |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 13 | #include <cpu/x86/msr.h> |
Arthur Heymans | 615818f | 2022-05-31 21:33:43 +0200 | [diff] [blame] | 14 | #include <cpu/x86/mtrr.h> |
Kyösti Mälkki | b2a5f0b | 2019-08-04 19:54:32 +0300 | [diff] [blame] | 15 | #include <cpu/x86/smm.h> |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 16 | #include <device/device.h> |
Patrick Rudolph | e56189c | 2018-04-18 10:11:59 +0200 | [diff] [blame] | 17 | #include <device/pci_ops.h> |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 18 | #include <soc/cpu.h> |
Marshall Dawson | 0814b12 | 2018-01-10 11:35:24 -0700 | [diff] [blame] | 19 | #include <soc/iomap.h> |
Arthur Heymans | 615818f | 2022-05-31 21:33:43 +0200 | [diff] [blame] | 20 | #include <soc/northbridge.h> |
| 21 | #include <soc/pci_devs.h> |
| 22 | #include <soc/smi.h> |
Felix Held | d27ef5b | 2021-10-20 20:18:12 +0200 | [diff] [blame] | 23 | #include <types.h> |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 24 | |
| 25 | /* |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 26 | * MP and SMM loading initialization. |
| 27 | */ |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 28 | |
| 29 | /* |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 30 | * Do essential initialization tasks before APs can be fired up - |
| 31 | * |
| 32 | * 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This |
| 33 | * creates the MTRR solution that the APs will use. Otherwise APs will try to |
| 34 | * apply the incomplete solution as the BSP is calculating it. |
| 35 | */ |
| 36 | static void pre_mp_init(void) |
| 37 | { |
Arthur Heymans | 615818f | 2022-05-31 21:33:43 +0200 | [diff] [blame] | 38 | const msr_t syscfg = rdmsr(SYSCFG_MSR); |
| 39 | if (syscfg.lo & SYSCFG_MSR_TOM2WB) |
| 40 | x86_setup_mtrrs_with_detect_no_above_4gb(); |
| 41 | else |
| 42 | x86_setup_mtrrs_with_detect(); |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 43 | x86_mtrr_check(); |
| 44 | } |
| 45 | |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 46 | static const struct mp_ops mp_ops = { |
| 47 | .pre_mp_init = pre_mp_init, |
| 48 | .get_cpu_count = get_cpu_count, |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 49 | .get_smm_info = get_smm_info, |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 50 | .relocation_handler = smm_relocation_handler, |
Kyösti Mälkki | 87e6796 | 2020-05-31 09:59:14 +0300 | [diff] [blame] | 51 | .post_mp_init = global_smi_enable, |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 52 | }; |
| 53 | |
Kyösti Mälkki | 79e12ab | 2020-05-31 09:21:07 +0300 | [diff] [blame] | 54 | void mp_init_cpus(struct bus *cpu_bus) |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 55 | { |
Felix Held | 28a0a14 | 2021-11-02 17:15:58 +0100 | [diff] [blame] | 56 | if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) |
| 57 | die_with_post_code(POST_HW_INIT_FAILURE, |
| 58 | "mp_init_with_smm failed. Halting.\n"); |
Marshall Dawson | 8f031d8 | 2018-04-09 22:15:06 -0600 | [diff] [blame] | 59 | |
| 60 | /* The flash is now no longer cacheable. Reset to WP for performance. */ |
Felix Held | 199b10f | 2022-08-13 00:29:23 +0200 | [diff] [blame] | 61 | mtrr_use_temp_range(FLASH_BELOW_4GB_MAPPING_REGION_BASE, |
| 62 | FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT); |
Marshall Dawson | 2e49cf12 | 2018-08-03 17:05:22 -0600 | [diff] [blame] | 63 | |
| 64 | set_warm_reset_flag(); |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 65 | } |
Marshall Dawson | 178e65d | 2017-10-20 13:20:25 -0600 | [diff] [blame] | 66 | |
Marshall Dawson | 74473ec | 2018-08-05 10:42:17 -0600 | [diff] [blame] | 67 | static void model_15_init(struct device *dev) |
| 68 | { |
| 69 | check_mca(); |
Marshall Dawson | 638bd13 | 2018-09-14 10:16:40 -0600 | [diff] [blame] | 70 | |
| 71 | /* |
| 72 | * Per AMD, sync an undocumented MSR with the PSP base address. |
| 73 | * Experiments showed that if you write to the MSR after it has |
| 74 | * been previously programmed, it causes a general protection fault. |
| 75 | * Also, the MSR survives warm reset and S3 cycles, so we need to |
| 76 | * test if it was previously written before writing to it. |
| 77 | */ |
| 78 | msr_t psp_msr; |
| 79 | uint32_t psp_bar; /* Note: NDA BKDG names this 32-bit register BAR3 */ |
| 80 | psp_bar = pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4); |
| 81 | psp_bar &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; |
Felix Held | e09294f | 2021-02-17 22:22:21 +0100 | [diff] [blame] | 82 | psp_msr = rdmsr(PSP_ADDR_MSR); |
Marshall Dawson | 638bd13 | 2018-09-14 10:16:40 -0600 | [diff] [blame] | 83 | if (psp_msr.lo == 0) { |
| 84 | psp_msr.lo = psp_bar; |
Felix Held | e09294f | 2021-02-17 22:22:21 +0100 | [diff] [blame] | 85 | wrmsr(PSP_ADDR_MSR, psp_msr); |
Marshall Dawson | 638bd13 | 2018-09-14 10:16:40 -0600 | [diff] [blame] | 86 | } |
Marshall Dawson | 178e65d | 2017-10-20 13:20:25 -0600 | [diff] [blame] | 87 | } |
| 88 | |
| 89 | static struct device_operations cpu_dev_ops = { |
| 90 | .init = model_15_init, |
| 91 | }; |
| 92 | |
| 93 | static struct cpu_device_id cpu_table[] = { |
Richard Spiegel | 9247e86 | 2019-06-28 09:18:47 -0700 | [diff] [blame] | 94 | { X86_VENDOR_AMD, 0x660f01 }, |
Marshall Dawson | 178e65d | 2017-10-20 13:20:25 -0600 | [diff] [blame] | 95 | { X86_VENDOR_AMD, 0x670f00 }, |
| 96 | { 0, 0 }, |
| 97 | }; |
| 98 | |
| 99 | static const struct cpu_driver model_15 __cpu_driver = { |
| 100 | .ops = &cpu_dev_ops, |
| 101 | .id_table = cpu_table, |
| 102 | }; |