Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 2 | |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 3 | #include <amdblocks/smm.h> |
Felix Held | 285dd6e | 2021-02-17 22:16:40 +0100 | [diff] [blame^] | 4 | #include <cpu/amd/msr.h> |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 5 | #include <cpu/cpu.h> |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 6 | #include <cpu/x86/mp.h> |
| 7 | #include <cpu/x86/mtrr.h> |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 8 | #include <cpu/x86/msr.h> |
Kyösti Mälkki | b2a5f0b | 2019-08-04 19:54:32 +0300 | [diff] [blame] | 9 | #include <cpu/x86/smm.h> |
Marshall Dawson | 178e65d | 2017-10-20 13:20:25 -0600 | [diff] [blame] | 10 | #include <cpu/x86/lapic.h> |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 11 | #include <device/device.h> |
Patrick Rudolph | e56189c | 2018-04-18 10:11:59 +0200 | [diff] [blame] | 12 | #include <device/pci_ops.h> |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 13 | #include <soc/pci_devs.h> |
| 14 | #include <soc/cpu.h> |
| 15 | #include <soc/northbridge.h> |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 16 | #include <soc/smi.h> |
Marshall Dawson | 0814b12 | 2018-01-10 11:35:24 -0700 | [diff] [blame] | 17 | #include <soc/iomap.h> |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 18 | #include <console/console.h> |
| 19 | |
| 20 | /* |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 21 | * MP and SMM loading initialization. |
| 22 | */ |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 23 | |
| 24 | /* |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 25 | * Do essential initialization tasks before APs can be fired up - |
| 26 | * |
| 27 | * 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This |
| 28 | * creates the MTRR solution that the APs will use. Otherwise APs will try to |
| 29 | * apply the incomplete solution as the BSP is calculating it. |
| 30 | */ |
| 31 | static void pre_mp_init(void) |
| 32 | { |
| 33 | x86_setup_mtrrs_with_detect(); |
| 34 | x86_mtrr_check(); |
| 35 | } |
| 36 | |
| 37 | static int get_cpu_count(void) |
| 38 | { |
Martin Roth | 1956a00 | 2018-10-30 22:31:40 -0600 | [diff] [blame] | 39 | return (pci_read_config16(SOC_HT_DEV, D18F0_CPU_CNT) & CPU_CNT_MASK) |
Richard Spiegel | 41baf0c | 2018-10-22 13:57:18 -0700 | [diff] [blame] | 40 | + 1; |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 41 | } |
| 42 | |
| 43 | static const struct mp_ops mp_ops = { |
| 44 | .pre_mp_init = pre_mp_init, |
| 45 | .get_cpu_count = get_cpu_count, |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 46 | .get_smm_info = get_smm_info, |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 47 | .relocation_handler = smm_relocation_handler, |
Kyösti Mälkki | 87e6796 | 2020-05-31 09:59:14 +0300 | [diff] [blame] | 48 | .post_mp_init = global_smi_enable, |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 49 | }; |
| 50 | |
Kyösti Mälkki | 79e12ab | 2020-05-31 09:21:07 +0300 | [diff] [blame] | 51 | void mp_init_cpus(struct bus *cpu_bus) |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 52 | { |
| 53 | /* Clear for take-off */ |
Kyösti Mälkki | 79e12ab | 2020-05-31 09:21:07 +0300 | [diff] [blame] | 54 | if (mp_init_with_smm(cpu_bus, &mp_ops) < 0) |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 55 | printk(BIOS_ERR, "MP initialization failure.\n"); |
Marshall Dawson | 8f031d8 | 2018-04-09 22:15:06 -0600 | [diff] [blame] | 56 | |
| 57 | /* The flash is now no longer cacheable. Reset to WP for performance. */ |
| 58 | mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); |
Marshall Dawson | 2e49cf12 | 2018-08-03 17:05:22 -0600 | [diff] [blame] | 59 | |
| 60 | set_warm_reset_flag(); |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 61 | } |
Marshall Dawson | 178e65d | 2017-10-20 13:20:25 -0600 | [diff] [blame] | 62 | |
Marshall Dawson | 74473ec | 2018-08-05 10:42:17 -0600 | [diff] [blame] | 63 | static void model_15_init(struct device *dev) |
| 64 | { |
| 65 | check_mca(); |
Marshall Dawson | 178e65d | 2017-10-20 13:20:25 -0600 | [diff] [blame] | 66 | setup_lapic(); |
Marshall Dawson | 638bd13 | 2018-09-14 10:16:40 -0600 | [diff] [blame] | 67 | |
| 68 | /* |
| 69 | * Per AMD, sync an undocumented MSR with the PSP base address. |
| 70 | * Experiments showed that if you write to the MSR after it has |
| 71 | * been previously programmed, it causes a general protection fault. |
| 72 | * Also, the MSR survives warm reset and S3 cycles, so we need to |
| 73 | * test if it was previously written before writing to it. |
| 74 | */ |
| 75 | msr_t psp_msr; |
| 76 | uint32_t psp_bar; /* Note: NDA BKDG names this 32-bit register BAR3 */ |
| 77 | psp_bar = pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4); |
| 78 | psp_bar &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; |
Felix Held | aecca75 | 2021-02-08 22:14:17 +0100 | [diff] [blame] | 79 | psp_msr = rdmsr(MSR_PSP_ADDR); |
Marshall Dawson | 638bd13 | 2018-09-14 10:16:40 -0600 | [diff] [blame] | 80 | if (psp_msr.lo == 0) { |
| 81 | psp_msr.lo = psp_bar; |
Felix Held | aecca75 | 2021-02-08 22:14:17 +0100 | [diff] [blame] | 82 | wrmsr(MSR_PSP_ADDR, psp_msr); |
Marshall Dawson | 638bd13 | 2018-09-14 10:16:40 -0600 | [diff] [blame] | 83 | } |
Marshall Dawson | 178e65d | 2017-10-20 13:20:25 -0600 | [diff] [blame] | 84 | } |
| 85 | |
| 86 | static struct device_operations cpu_dev_ops = { |
| 87 | .init = model_15_init, |
| 88 | }; |
| 89 | |
| 90 | static struct cpu_device_id cpu_table[] = { |
Richard Spiegel | 9247e86 | 2019-06-28 09:18:47 -0700 | [diff] [blame] | 91 | { X86_VENDOR_AMD, 0x660f01 }, |
Marshall Dawson | 178e65d | 2017-10-20 13:20:25 -0600 | [diff] [blame] | 92 | { X86_VENDOR_AMD, 0x670f00 }, |
| 93 | { 0, 0 }, |
| 94 | }; |
| 95 | |
| 96 | static const struct cpu_driver model_15 __cpu_driver = { |
| 97 | .ops = &cpu_dev_ops, |
| 98 | .id_table = cpu_table, |
| 99 | }; |