amd/stoneyridge: Move model_15_init.c to cpu.c
Move the remaining model_15_init.c functionality to cpu.c, making it
similar to other soc implementations.
Change-Id: Ic8c62b09209fcdaa50ff8ffc7773ef155f979a1b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23724
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c
index 5042cbc..14b6881 100644
--- a/src/soc/amd/stoneyridge/cpu.c
+++ b/src/soc/amd/stoneyridge/cpu.c
@@ -18,6 +18,7 @@
#include <cpu/x86/mp.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic.h>
#include <cpu/amd/amdfam15.h>
#include <device/device.h>
#include <soc/pci_devs.h>
@@ -113,3 +114,33 @@
if (mp_init_with_smm(dev->link_list, &mp_ops) < 0)
printk(BIOS_ERR, "MP initialization failure.\n");
}
+
+static void model_15_init(device_t dev)
+{
+ printk(BIOS_DEBUG, "Model 15 Init.\n");
+
+ int i;
+ msr_t msr;
+
+ /* zero the machine check error status registers */
+ msr.lo = 0;
+ msr.hi = 0;
+ for (i = 0 ; i < 6 ; i++)
+ wrmsr(MCI_STATUS + (i * 4), msr);
+
+ setup_lapic();
+}
+
+static struct device_operations cpu_dev_ops = {
+ .init = model_15_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+ { X86_VENDOR_AMD, 0x670f00 },
+ { 0, 0 },
+};
+
+static const struct cpu_driver model_15 __cpu_driver = {
+ .ops = &cpu_dev_ops,
+ .id_table = cpu_table,
+};