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Angel Ponsae593872020-04-04 18:50:57 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Marshall Dawson9df969a2017-07-25 18:46:46 -06002
Kyösti Mälkki021c6212021-01-26 11:28:47 +02003#include <amdblocks/acpi.h>
Michał Żygowski5a662022019-12-02 17:02:00 +01004#include <amdblocks/biosram.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +02005#include <device/pci_ops.h>
Marshall Dawson18b477e2017-09-21 12:27:12 -06006#include <arch/cpu.h>
Kyösti Mälkkia963acd2019-08-16 20:34:25 +03007#include <arch/romstage.h>
Furquan Shaikh76cedd22020-05-02 10:24:23 -07008#include <acpi/acpi.h>
Marshall Dawsona7bfbbe2017-09-13 17:24:53 -06009#include <cpu/x86/msr.h>
10#include <cpu/x86/mtrr.h>
Kyösti Mälkkib2a5f0b2019-08-04 19:54:32 +030011#include <cpu/x86/smm.h>
Marshall Dawsona7bfbbe2017-09-13 17:24:53 -060012#include <cpu/amd/mtrr.h>
Marshall Dawson9df969a2017-07-25 18:46:46 -060013#include <cbmem.h>
Marshall Dawson18b477e2017-09-21 12:27:12 -060014#include <commonlib/helpers.h>
Marshall Dawson9df969a2017-07-25 18:46:46 -060015#include <console/console.h>
Marshall Dawson3e4e4c52017-11-10 16:08:37 -070016#include <device/device.h>
Marshall Dawson9df969a2017-07-25 18:46:46 -060017#include <program_loading.h>
Marshall Dawson8f2a7e02017-11-01 11:44:48 -060018#include <romstage_handoff.h>
Daniel Kurtzc6c89722018-05-24 17:57:37 -060019#include <elog.h>
Richard Spiegel0ad74ac2017-12-08 16:53:29 -070020#include <amdblocks/agesawrapper.h>
21#include <amdblocks/agesawrapper_call.h>
Marshall Dawson9df969a2017-07-25 18:46:46 -060022#include <soc/northbridge.h>
Felix Helddba32292020-03-31 23:54:44 +020023#include <soc/pci_devs.h>
Marc Jonesdfeb1c42017-08-07 19:08:24 -060024#include <soc/southbridge.h>
Marshall Dawson9df969a2017-07-25 18:46:46 -060025#include <amdblocks/psp.h>
26
Elyes HAOUASc3385072019-03-21 15:38:06 +010027#include "chip.h"
28
Kyösti Mälkki9e591c42021-01-09 12:37:25 +020029void __weak mainboard_romstage_entry(void)
Martin Roth2c3e3ef2018-04-11 16:35:08 -060030{
31 /* By default, don't do anything */
32}
33
Raul E Rangel873b4e72018-06-12 10:53:55 -060034static void agesa_call(void)
35{
36 post_code(0x37);
Kyösti Mälkki6e512c42018-06-14 06:57:05 +030037 do_agesawrapper(AMD_INIT_RESET, "amdinitreset");
Raul E Rangel873b4e72018-06-12 10:53:55 -060038
39 post_code(0x38);
40 /* APs will not exit amdinitearly */
Kyösti Mälkki6e512c42018-06-14 06:57:05 +030041 do_agesawrapper(AMD_INIT_EARLY, "amdinitearly");
Raul E Rangel873b4e72018-06-12 10:53:55 -060042}
43
44static void bsp_agesa_call(void)
45{
46 set_ap_entry_ptr(agesa_call); /* indicate the path to the AP */
47 agesa_call();
48}
49
Marshall Dawson9df969a2017-07-25 18:46:46 -060050asmlinkage void car_stage_entry(void)
51{
Marshall Dawson18b477e2017-09-21 12:27:12 -060052 struct postcar_frame pcf;
53 uintptr_t top_of_ram;
Marshall Dawsona7bfbbe2017-09-13 17:24:53 -060054 msr_t base, mask;
55 msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
56 int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT;
Kyösti Mälkki9e591c42021-01-09 12:37:25 +020057 int s3_resume = acpi_is_wakeup_s3();
Marshall Dawsona7bfbbe2017-09-13 17:24:53 -060058 int i;
59
Marshall Dawson9df969a2017-07-25 18:46:46 -060060 console_init();
61
Felix Helddba32292020-03-31 23:54:44 +020062 soc_enable_psp_early();
Julius Wernercd49cce2019-03-05 16:53:33 -080063 if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW))
Felix Helddba32292020-03-31 23:54:44 +020064 psp_load_named_blob(BLOB_SMU_FW, "smu_fw");
Raul E Rangel873b4e72018-06-12 10:53:55 -060065
Kyösti Mälkki9e591c42021-01-09 12:37:25 +020066 mainboard_romstage_entry();
Kyösti Mälkki7f50afb2019-09-11 17:12:26 +030067 elog_boot_notify(s3_resume);
Raul E Rangel873b4e72018-06-12 10:53:55 -060068
69 bsp_agesa_call();
70
Marshall Dawson8f2a7e02017-11-01 11:44:48 -060071 if (!s3_resume) {
72 post_code(0x40);
Kyösti Mälkki6e512c42018-06-14 06:57:05 +030073 do_agesawrapper(AMD_INIT_POST, "amdinitpost");
Marshall Dawson9df969a2017-07-25 18:46:46 -060074
Marshall Dawson8f2a7e02017-11-01 11:44:48 -060075 post_code(0x41);
76 /*
77 * TODO: This is a hack to work around current AGESA behavior.
78 * AGESA needs to change to reflect that coreboot owns
79 * the MTRRs.
80 *
81 * After setting up DRAM, AGESA also completes the configuration
82 * of the MTRRs, setting regions to WB. Anything written to
Elyes HAOUASba4dbf82021-01-16 15:02:17 +010083 * memory between now and when CAR is dismantled will be
Marshall Dawson8f2a7e02017-11-01 11:44:48 -060084 * in cache and lost. For now, set the regions UC to ensure
85 * the writes get to DRAM.
86 */
87 for (i = 0 ; i < vmtrrs ; i++) {
88 base = rdmsr(MTRR_PHYS_BASE(i));
89 mask = rdmsr(MTRR_PHYS_MASK(i));
90 if (!(mask.lo & MTRR_PHYS_MASK_VALID))
91 continue;
Marshall Dawsona7bfbbe2017-09-13 17:24:53 -060092
Marshall Dawson8f2a7e02017-11-01 11:44:48 -060093 if ((base.lo & 0x7) == MTRR_TYPE_WRBACK) {
94 base.lo &= ~0x7;
95 base.lo |= MTRR_TYPE_UNCACHEABLE;
96 wrmsr(MTRR_PHYS_BASE(i), base);
97 }
Marshall Dawsona7bfbbe2017-09-13 17:24:53 -060098 }
Marshall Dawson8f2a7e02017-11-01 11:44:48 -060099 /* Disable WB from to region 4GB-TOM2. */
100 msr_t sys_cfg = rdmsr(SYSCFG_MSR);
101 sys_cfg.lo &= ~SYSCFG_MSR_TOM2WB;
102 wrmsr(SYSCFG_MSR, sys_cfg);
103 } else {
104 printk(BIOS_INFO, "S3 detected\n");
105 post_code(0x60);
Kyösti Mälkki6e512c42018-06-14 06:57:05 +0300106 do_agesawrapper(AMD_INIT_RESUME, "amdinitresume");
Marshall Dawson8f2a7e02017-11-01 11:44:48 -0600107
108 post_code(0x61);
Marshall Dawsona7bfbbe2017-09-13 17:24:53 -0600109 }
Marshall Dawson9df969a2017-07-25 18:46:46 -0600110
111 post_code(0x42);
Marshall Dawsona7bfbbe2017-09-13 17:24:53 -0600112 psp_notify_dram();
113
114 post_code(0x43);
Marshall Dawson8f2a7e02017-11-01 11:44:48 -0600115 if (cbmem_recovery(s3_resume))
116 printk(BIOS_CRIT, "Failed to recover cbmem\n");
117 if (romstage_handoff_init(s3_resume))
118 printk(BIOS_ERR, "Failed to set romstage handoff data\n");
Marshall Dawson9df969a2017-07-25 18:46:46 -0600119
Kyösti Mälkki7cdb0472019-08-08 11:16:06 +0300120 if (CONFIG(SMM_TSEG))
121 smm_list_regions();
122
Marshall Dawson18b477e2017-09-21 12:27:12 -0600123 post_code(0x44);
Kyösti Mälkki6e2d0c12019-06-28 10:08:51 +0300124 if (postcar_frame_init(&pcf, 0))
Marshall Dawson18b477e2017-09-21 12:27:12 -0600125 die("Unable to initialize postcar frame.\n");
126
Marshall Dawson9df969a2017-07-25 18:46:46 -0600127 /*
Marshall Dawson18b477e2017-09-21 12:27:12 -0600128 * We need to make sure ramstage will be run cached. At this point exact
129 * location of ramstage in cbmem is not known. Instruct postcar to cache
130 * 16 megs under cbmem top which is a safe bet to cover ramstage.
Marshall Dawson9df969a2017-07-25 18:46:46 -0600131 */
Marshall Dawson18b477e2017-09-21 12:27:12 -0600132 top_of_ram = (uintptr_t) cbmem_top();
Marshall Dawson18b477e2017-09-21 12:27:12 -0600133 postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB,
134 MTRR_TYPE_WRBACK);
Marshall Dawson9df969a2017-07-25 18:46:46 -0600135
Marshall Dawson18b477e2017-09-21 12:27:12 -0600136 /* Cache the memory-mapped boot media. */
Nico Huber6ea67752018-05-27 14:37:52 +0200137 postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
Marshall Dawson9df969a2017-07-25 18:46:46 -0600138
Subrata Banik3eff0372019-09-10 15:51:17 +0530139 /* Cache the TSEG region */
140 postcar_enable_tseg_cache(&pcf);
Marshall Dawson18b477e2017-09-21 12:27:12 -0600141
142 post_code(0x45);
143 run_postcar_phase(&pcf);
144
145 post_code(0x50); /* Should never see this post code. */
Marshall Dawson9df969a2017-07-25 18:46:46 -0600146}
Richard Spiegel67c2a7b2017-11-09 16:04:35 -0700147
148void SetMemParams(AMD_POST_PARAMS *PostParams)
149{
150 const struct soc_amd_stoneyridge_config *cfg;
Kyösti Mälkkie7377552018-06-21 16:20:55 +0300151 const struct device *dev = pcidev_path_on_root(GNB_DEVFN);
Richard Spiegel67c2a7b2017-11-09 16:04:35 -0700152
153 if (!dev || !dev->chip_info) {
Julius Wernere9665952022-01-21 17:06:20 -0800154 printk(BIOS_ERR, "Cannot find SoC devicetree config\n");
Aaron Durbin36dbf1d2017-11-10 13:16:23 -0700155 /* In case of a BIOS error, only attempt to set UMA. */
Julius Wernercd49cce2019-03-05 16:53:33 -0800156 PostParams->MemConfig.UmaMode = CONFIG(GFXUMA) ?
Aaron Durbin36dbf1d2017-11-10 13:16:23 -0700157 UMA_AUTO : UMA_NONE;
Richard Spiegel67c2a7b2017-11-09 16:04:35 -0700158 return;
159 }
160
161 cfg = dev->chip_info;
Aaron Durbin36dbf1d2017-11-10 13:16:23 -0700162
Richard Spiegel67c2a7b2017-11-09 16:04:35 -0700163 PostParams->MemConfig.EnableMemClr = cfg->dram_clear_on_reset;
Aaron Durbin36dbf1d2017-11-10 13:16:23 -0700164
165 switch (cfg->uma_mode) {
166 case UMAMODE_NONE:
167 PostParams->MemConfig.UmaMode = UMA_NONE;
168 break;
169 case UMAMODE_SPECIFIED_SIZE:
170 PostParams->MemConfig.UmaMode = UMA_SPECIFIED;
171 /* 64 KiB blocks. */
172 PostParams->MemConfig.UmaSize = cfg->uma_size / (64 * KiB);
173 break;
174 case UMAMODE_AUTO_LEGACY:
175 PostParams->MemConfig.UmaMode = UMA_AUTO;
176 PostParams->MemConfig.UmaVersion = UMA_LEGACY;
177 break;
178 case UMAMODE_AUTO_NON_LEGACY:
179 PostParams->MemConfig.UmaMode = UMA_AUTO;
180 PostParams->MemConfig.UmaVersion = UMA_NON_LEGACY;
181 break;
182 }
Richard Spiegel67c2a7b2017-11-09 16:04:35 -0700183}
Richard Spiegeldd9b1d12018-09-20 14:50:11 -0700184
185void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly)
186{
187 const struct soc_amd_stoneyridge_config *cfg;
Kyösti Mälkkie7377552018-06-21 16:20:55 +0300188 const struct device *dev = pcidev_path_on_root(GNB_DEVFN);
Richard Spiegeldd9b1d12018-09-20 14:50:11 -0700189 struct _PLATFORM_CONFIGURATION *platform;
190
191 if (!dev || !dev->chip_info) {
Julius Wernere9665952022-01-21 17:06:20 -0800192 printk(BIOS_WARNING, "Cannot find SoC devicetree"
Richard Spiegeldd9b1d12018-09-20 14:50:11 -0700193 " config, STAPM unchanged\n");
194 return;
195 }
196 cfg = dev->chip_info;
197 platform = &InitEarly->PlatformConfig;
Richard Spiegelde5d0402018-10-11 08:15:43 -0700198 if ((cfg->stapm_percent) && (cfg->stapm_time_ms) &&
199 (cfg->stapm_power_mw)) {
Richard Spiegeldd9b1d12018-09-20 14:50:11 -0700200 platform->PlatStapmConfig.CfgStapmScalar = cfg->stapm_percent;
201 platform->PlatStapmConfig.CfgStapmTimeConstant =
Richard Spiegelde5d0402018-10-11 08:15:43 -0700202 cfg->stapm_time_ms;
203 platform->PkgPwrLimitDC = cfg->stapm_power_mw;
204 platform->PkgPwrLimitAC = cfg->stapm_power_mw;
Richard Spiegeldd9b1d12018-09-20 14:50:11 -0700205 platform->PlatStapmConfig.CfgStapmBoost = StapmBoostEnabled;
206 }
207}
Kyösti Mälkki021c6212021-01-26 11:28:47 +0200208
209static void migrate_power_state(int is_recovery)
210{
211 struct chipset_power_state *state;
212 state = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*state));
213 if (state) {
214 acpi_fill_pm_gpe_state(&state->gpe_state);
215 acpi_pm_gpe_add_events_print_events();
216 }
Kyösti Mälkki021c6212021-01-26 11:28:47 +0200217}
218ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state)