Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/pci.h> |
| 5 | #include <arch/io.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Richard Spiegel | 2bbc3dc | 2017-12-06 16:14:58 -0700 | [diff] [blame] | 7 | #include <amdblocks/amd_pci_util.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 8 | #include <pc80/i8259.h> |
Richard Spiegel | a800bdb | 2017-11-13 16:59:38 -0700 | [diff] [blame] | 9 | #include <soc/amd_pci_int_defs.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 10 | |
Aaron Durbin | 8dd4006 | 2017-11-03 11:50:14 -0600 | [diff] [blame] | 11 | const struct pirq_struct *pirq_data_ptr; |
| 12 | u32 pirq_data_size; |
| 13 | const u8 *intr_data_ptr; |
| 14 | const u8 *picr_data_ptr; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 15 | |
| 16 | /* |
| 17 | * Read the FCH PCI_INTR registers 0xC00/0xC01 at a |
| 18 | * given index and a given PIC (0) or IOAPIC (1) mode |
| 19 | */ |
| 20 | u8 read_pci_int_idx(u8 index, int mode) |
| 21 | { |
| 22 | outb((mode << 7) | index, PCI_INTR_INDEX); |
| 23 | return inb(PCI_INTR_DATA); |
| 24 | } |
| 25 | |
| 26 | /* |
| 27 | * Write a value to the FCH PCI_INTR registers 0xC00/0xC01 |
| 28 | * at a given index and PIC (0) or IOAPIC (1) mode |
| 29 | */ |
| 30 | void write_pci_int_idx(u8 index, int mode, u8 data) |
| 31 | { |
| 32 | outb((mode << 7) | index, PCI_INTR_INDEX); |
| 33 | outb(data, PCI_INTR_DATA); |
| 34 | } |
| 35 | |
| 36 | /* |
| 37 | * Write the FCH PCI_INTR registers 0xC00/0xC01 with values |
| 38 | * given in global variables intr_data and picr_data. |
| 39 | * These variables are defined in mainboard.c |
| 40 | */ |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 41 | void write_pci_int_table(void) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 42 | { |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 43 | uint8_t byte; |
| 44 | size_t i, limit; |
| 45 | const struct irq_idx_name *idx_name; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 46 | |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 47 | idx_name = sb_get_apic_reg_association(&limit); |
Richard Spiegel | 6c2ab06 | 2017-12-18 09:52:42 -0700 | [diff] [blame] | 48 | if (picr_data_ptr == NULL || intr_data_ptr == NULL || |
| 49 | idx_name == NULL) { |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 50 | printk(BIOS_ERR, "Warning: Can't write PCI_INTR 0xC00/0xC01" |
| 51 | " registers because\n" |
Richard Spiegel | 6c2ab06 | 2017-12-18 09:52:42 -0700 | [diff] [blame] | 52 | "'mainboard_picr_data' or 'mainboard_intr_data'" |
| 53 | " or 'irq_association'\ntables are NULL\n"); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 54 | return; |
| 55 | } |
| 56 | |
| 57 | /* PIC IRQ routine */ |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 58 | printk(BIOS_DEBUG, "PCI_INTR tables: Writing registers C00/C01 for" |
| 59 | " PCI IRQ routing:\n" |
Richard Spiegel | e89d444 | 2017-12-08 07:52:42 -0700 | [diff] [blame] | 60 | "PCI_INTR_INDEX\tname\t\t PIC mode" |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 61 | "\tAPIC mode\n"); |
| 62 | /* |
| 63 | * Iterate table idx_name, indexes outside the table are ignored |
| 64 | * (assumed not connected within the chip). For each iteration, |
| 65 | * get the register index "byte" and the name of the associated |
| 66 | * IRQ source for printing. |
| 67 | */ |
| 68 | for (i = 0 ; i < limit; i++) { |
| 69 | byte = idx_name[i].index; |
| 70 | write_pci_int_idx(byte, 0, (u8) picr_data_ptr[byte]); |
Richard Spiegel | e89d444 | 2017-12-08 07:52:42 -0700 | [diff] [blame] | 71 | printk(BIOS_DEBUG, "0x%02X\t\t%-20s 0x%02X\t", |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 72 | byte, idx_name[i].name, |
| 73 | read_pci_int_idx(byte, 0)); |
| 74 | write_pci_int_idx(byte, 1, (u8) intr_data_ptr[byte]); |
| 75 | printk(BIOS_DEBUG, "0x%02X\n", read_pci_int_idx(byte, 1)); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 76 | } |
| 77 | } |
| 78 | |
| 79 | /* |
| 80 | * Function to write the PCI config space Interrupt |
| 81 | * registers based on the values given in PCI_INTR |
| 82 | * table at I/O port 0xC00/0xC01 |
| 83 | */ |
| 84 | void write_pci_cfg_irqs(void) |
| 85 | { |
Elyes HAOUAS | 0f5957a | 2018-05-22 10:58:50 +0200 | [diff] [blame] | 86 | struct device *dev = NULL; /* Our current device to route IRQs */ |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 87 | struct device *target_dev = NULL; /* the bridge a device may be |
| 88 | * connected to */ |
| 89 | u16 int_pin = 0; |
| 90 | u16 target_pin = 0; |
| 91 | u16 int_line = 0; |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 92 | u16 pci_intr_idx = 0; /* Index into PCI_INTR table, 0xC00/0xC01 */ |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 93 | u16 devfn = 0; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 94 | u32 i = 0; |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 95 | size_t limit; |
| 96 | const struct irq_idx_name *idx_name; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 97 | |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 98 | idx_name = sb_get_apic_reg_association(&limit); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 99 | if (pirq_data_ptr == NULL) { |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 100 | printk(BIOS_WARNING, "Can't write PCI IRQ assignments" |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 101 | " because 'mainboard_pirq_data' structure does" |
| 102 | " not exist\n"); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 103 | return; |
| 104 | } |
| 105 | |
| 106 | /* Populate the PCI cfg space header with the IRQ assignment */ |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 107 | printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ" |
| 108 | " assignments\n"); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 109 | |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 110 | for (dev = all_devices ; dev ; dev = dev->next) { |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 111 | /* |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 112 | * Step 1: Get INT_PIN and device structure to look for in the |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 113 | * PCI_INTR table pirq_data |
| 114 | */ |
| 115 | target_dev = NULL; |
| 116 | target_pin = get_pci_irq_pins(dev, &target_dev); |
| 117 | if (target_dev == NULL) |
| 118 | continue; |
| 119 | |
| 120 | if (target_pin < 1) |
| 121 | continue; |
| 122 | |
| 123 | /* Get the original INT_PIN for record keeping */ |
| 124 | int_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN); |
| 125 | if (int_pin < 1 || int_pin > 4) |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 126 | continue; /* Device has invalid INT_PIN - skip */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 127 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 128 | devfn = target_dev->path.pci.devfn; |
| 129 | |
| 130 | /* |
| 131 | * Step 2: Use the INT_PIN and DevFn number to find the PCI_INTR |
| 132 | * register (0xC00) index for this device |
| 133 | */ |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 134 | pci_intr_idx = 0xbad; /* Will check to make sure it changed */ |
| 135 | for (i = 0 ; i < pirq_data_size ; i++) { |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 136 | if (pirq_data_ptr[i].devfn != devfn) |
| 137 | continue; |
| 138 | |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 139 | /* PIN_A is idx0 in pirq_data array but 1 in PCI reg */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 140 | pci_intr_idx = pirq_data_ptr[i].PIN[target_pin - 1]; |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 141 | printk(BIOS_SPEW, "\tFound this device in pirq_data" |
| 142 | " table entry %d\n", i); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 143 | break; |
| 144 | } |
| 145 | |
| 146 | /* |
| 147 | * Step 3: Make sure we got a valid index and use it to get |
| 148 | * the IRQ number from the PCI_INTR register table |
| 149 | */ |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 150 | if (pci_intr_idx == 0xbad) { |
| 151 | /* Not on a bridge or in pirq_data table, skip it */ |
| 152 | printk(BIOS_SPEW, "PCI Devfn (0x%x) not found in" |
| 153 | " pirq_data table\n", devfn); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 154 | continue; |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 155 | } else if (pci_intr_idx == 0x1f) { |
| 156 | /* Index found is not defined */ |
| 157 | printk(BIOS_SPEW, "Got index 0x1F (Not Connected)," |
| 158 | " perhaps this device was" |
| 159 | " defined wrong?\n"); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 160 | continue; |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 161 | } |
| 162 | /* |
| 163 | * Find the name associated with register [pci_intr_idx] |
| 164 | * and print information. |
| 165 | */ |
| 166 | for (i = 0; i < limit; i++) { |
| 167 | if (idx_name[i].index == pci_intr_idx) |
| 168 | break; |
| 169 | } |
| 170 | if (i == limit) { |
| 171 | printk(BIOS_SPEW, "Got register index 0x%02x" |
| 172 | " undefined in table irq_idx_name,\n" |
| 173 | " perhaps this device was" |
| 174 | " defined wrong?\n", pci_intr_idx); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 175 | continue; |
| 176 | } |
| 177 | |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 178 | /* Find the value to program into the INT_LINE register from |
| 179 | * the PCI_INTR registers |
| 180 | */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 181 | int_line = read_pci_int_idx(pci_intr_idx, 0); |
| 182 | if (int_line == PIRQ_NC) { /* The IRQ found is disabled */ |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 183 | printk(BIOS_SPEW, "Got IRQ 0x1F (disabled), perhaps" |
| 184 | " this device was defined wrong?\n"); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 185 | continue; |
| 186 | } |
| 187 | |
| 188 | /* |
| 189 | * Step 4: Program the INT_LINE register in this device's |
| 190 | * PCI config space with the IRQ number we found in step 3 |
| 191 | * and make it Level Triggered |
| 192 | */ |
| 193 | pci_write_config8(dev, PCI_INTERRUPT_LINE, int_line); |
| 194 | |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 195 | /* Set IRQ to level triggered since used by a PCI device */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 196 | i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED); |
| 197 | |
| 198 | /* |
| 199 | * Step 5: Print out debug info and move on to next device |
| 200 | */ |
| 201 | printk(BIOS_SPEW, "\tOrig INT_PIN\t: %d (%s)\n", |
| 202 | int_pin, pin_to_str(int_pin)); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 203 | printk(BIOS_SPEW, "\tPCI_INTR idx\t: 0x%02x (%s)\n" |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 204 | "\tINT_LINE\t: 0x%X (IRQ %d)\n", |
| 205 | pci_intr_idx, idx_name[i].name, |
| 206 | int_line, int_line); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 207 | } /* for (dev = all_devices) */ |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 208 | printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space" |
| 209 | " IRQ assignments\n"); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 210 | } |