Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Sage Electronic Engineering, LLC. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <console/console.h> |
| 17 | #include <device/pci.h> |
| 18 | #include <arch/io.h> |
| 19 | #include <string.h> |
| 20 | #include <amd_pci_util.h> |
| 21 | #include <pc80/i8259.h> |
| 22 | #include <amd_pci_int_defs.h> |
| 23 | #include <amd_pci_int_types.h> |
| 24 | |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame^] | 25 | const struct pirq_struct *pirq_data_ptr = NULL; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 26 | u32 pirq_data_size = 0; |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame^] | 27 | const u8 *intr_data_ptr = NULL; |
| 28 | const u8 *picr_data_ptr = NULL; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 29 | |
| 30 | /* |
| 31 | * Read the FCH PCI_INTR registers 0xC00/0xC01 at a |
| 32 | * given index and a given PIC (0) or IOAPIC (1) mode |
| 33 | */ |
| 34 | u8 read_pci_int_idx(u8 index, int mode) |
| 35 | { |
| 36 | outb((mode << 7) | index, PCI_INTR_INDEX); |
| 37 | return inb(PCI_INTR_DATA); |
| 38 | } |
| 39 | |
| 40 | /* |
| 41 | * Write a value to the FCH PCI_INTR registers 0xC00/0xC01 |
| 42 | * at a given index and PIC (0) or IOAPIC (1) mode |
| 43 | */ |
| 44 | void write_pci_int_idx(u8 index, int mode, u8 data) |
| 45 | { |
| 46 | outb((mode << 7) | index, PCI_INTR_INDEX); |
| 47 | outb(data, PCI_INTR_DATA); |
| 48 | } |
| 49 | |
| 50 | /* |
| 51 | * Write the FCH PCI_INTR registers 0xC00/0xC01 with values |
| 52 | * given in global variables intr_data and picr_data. |
| 53 | * These variables are defined in mainboard.c |
| 54 | */ |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame^] | 55 | void write_pci_int_table(void) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 56 | { |
| 57 | u8 byte; |
| 58 | |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame^] | 59 | if (picr_data_ptr == NULL || intr_data_ptr == NULL) { |
| 60 | printk(BIOS_ERR, "Warning: Can't write PCI_INTR 0xC00/0xC01" |
| 61 | " registers because\n" |
| 62 | "'mainboard_picr_data' or 'mainboard_intr_data'" |
| 63 | " tables are NULL\n"); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 64 | return; |
| 65 | } |
| 66 | |
| 67 | /* PIC IRQ routine */ |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame^] | 68 | printk(BIOS_DEBUG, "PCI_INTR tables: Writing registers C00/C01 for PIC" |
| 69 | " mode PCI IRQ routing:\n" |
| 70 | "\tPCI_INTR_INDEX\t\tPCI_INTR_DATA\n"); |
| 71 | for (byte = 0 ; byte < FCH_INT_TABLE_SIZE ; byte++) { |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 72 | if (intr_types[byte]) { |
| 73 | write_pci_int_idx(byte, 0, (u8) picr_data_ptr[byte]); |
| 74 | printk(BIOS_DEBUG, "\t0x%02X %s\t: 0x%02X\n", |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame^] | 75 | byte, intr_types[byte], |
| 76 | read_pci_int_idx(byte, 0)); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 77 | } |
| 78 | } |
| 79 | |
| 80 | /* APIC IRQ routine */ |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame^] | 81 | printk(BIOS_DEBUG, "PCI_INTR tables: Writing registers C00/C01 for APIC" |
| 82 | " mode PCI IRQ routing:\n" |
| 83 | "\tPCI_INTR_INDEX\t\tPCI_INTR_DATA\n"); |
| 84 | for (byte = 0 ; byte < FCH_INT_TABLE_SIZE ; byte++) { |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 85 | if (intr_types[byte]) { |
| 86 | write_pci_int_idx(byte, 1, (u8) intr_data_ptr[byte]); |
| 87 | printk(BIOS_DEBUG, "\t0x%02X %s\t: 0x%02X\n", |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame^] | 88 | byte, intr_types[byte], |
| 89 | read_pci_int_idx(byte, 1)); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 90 | } |
| 91 | } |
| 92 | } |
| 93 | |
| 94 | /* |
| 95 | * Function to write the PCI config space Interrupt |
| 96 | * registers based on the values given in PCI_INTR |
| 97 | * table at I/O port 0xC00/0xC01 |
| 98 | */ |
| 99 | void write_pci_cfg_irqs(void) |
| 100 | { |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame^] | 101 | device_t dev = NULL; /* Our current device to route IRQs */ |
| 102 | device_t target_dev = NULL; /* to bridge a device may be connected to */ |
| 103 | u16 int_pin = 0; /* Value of the INT_PIN register 0x3D */ |
| 104 | u16 target_pin = 0; /* Pin we will search our tables for */ |
| 105 | u16 int_line = 0; /* IRQ # read from PCI_INTR tbl and write to 3C */ |
| 106 | u16 pci_intr_idx = 0; /* Index into PCI_INTR table, 0xC00/0xC01 */ |
| 107 | u8 bus = 0; /* A PCI Device Bus number */ |
| 108 | u16 devfn = 0; /* A PCI Device and Function number */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 109 | u8 bridged_device = 0; /* This device is on a PCI bridge */ |
| 110 | u32 i = 0; |
| 111 | |
| 112 | if (pirq_data_ptr == NULL) { |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame^] | 113 | printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments" |
| 114 | " because 'mainboard_pirq_data' structure does" |
| 115 | " not exist\n"); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 116 | return; |
| 117 | } |
| 118 | |
| 119 | /* Populate the PCI cfg space header with the IRQ assignment */ |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame^] | 120 | printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ" |
| 121 | " assignments\n"); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 122 | |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame^] | 123 | for (dev = all_devices ; dev ; dev = dev->next) { |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 124 | /* |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame^] | 125 | * Step 1: Get INT_PIN and device structure to look for in the |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 126 | * PCI_INTR table pirq_data |
| 127 | */ |
| 128 | target_dev = NULL; |
| 129 | target_pin = get_pci_irq_pins(dev, &target_dev); |
| 130 | if (target_dev == NULL) |
| 131 | continue; |
| 132 | |
| 133 | if (target_pin < 1) |
| 134 | continue; |
| 135 | |
| 136 | /* Get the original INT_PIN for record keeping */ |
| 137 | int_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN); |
| 138 | if (int_pin < 1 || int_pin > 4) |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame^] | 139 | continue; /* Device has invalid INT_PIN - skip */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 140 | |
| 141 | bus = target_dev->bus->secondary; |
| 142 | devfn = target_dev->path.pci.devfn; |
| 143 | |
| 144 | /* |
| 145 | * Step 2: Use the INT_PIN and DevFn number to find the PCI_INTR |
| 146 | * register (0xC00) index for this device |
| 147 | */ |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame^] | 148 | pci_intr_idx = 0xbad; /* Will check to make sure it changed */ |
| 149 | for (i = 0 ; i < pirq_data_size ; i++) { |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 150 | if (pirq_data_ptr[i].devfn != devfn) |
| 151 | continue; |
| 152 | |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame^] | 153 | /* PIN_A is idx0 in pirq_data array but 1 in PCI reg */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 154 | pci_intr_idx = pirq_data_ptr[i].PIN[target_pin - 1]; |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame^] | 155 | printk(BIOS_SPEW, "\tFound this device in pirq_data" |
| 156 | " table entry %d\n", i); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 157 | break; |
| 158 | } |
| 159 | |
| 160 | /* |
| 161 | * Step 3: Make sure we got a valid index and use it to get |
| 162 | * the IRQ number from the PCI_INTR register table |
| 163 | */ |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame^] | 164 | if (pci_intr_idx == 0xbad) { |
| 165 | /* Not on a bridge or in pirq_data table, skip it */ |
| 166 | printk(BIOS_SPEW, "PCI Devfn (0x%x) not found in" |
| 167 | " pirq_data table\n", devfn); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 168 | continue; |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame^] | 169 | } else if (pci_intr_idx == 0x1f) { |
| 170 | /* Index found is not defined */ |
| 171 | printk(BIOS_SPEW, "Got index 0x1F (Not Connected)," |
| 172 | " perhaps this device was" |
| 173 | " defined wrong?\n"); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 174 | continue; |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame^] | 175 | } else if (pci_intr_idx >= FCH_INT_TABLE_SIZE) { |
| 176 | /* Index out of bounds */ |
| 177 | printk(BIOS_ERR, "%s: got 0xC00/0xC01 table index" |
| 178 | " 0x%x, max is 0x%x\n", __func__, |
| 179 | pci_intr_idx, FCH_INT_TABLE_SIZE); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 180 | continue; |
| 181 | } |
| 182 | |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame^] | 183 | /* Find the value to program into the INT_LINE register from |
| 184 | * the PCI_INTR registers |
| 185 | */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 186 | int_line = read_pci_int_idx(pci_intr_idx, 0); |
| 187 | if (int_line == PIRQ_NC) { /* The IRQ found is disabled */ |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame^] | 188 | printk(BIOS_SPEW, "Got IRQ 0x1F (disabled), perhaps" |
| 189 | " this device was defined wrong?\n"); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 190 | continue; |
| 191 | } |
| 192 | |
| 193 | /* |
| 194 | * Step 4: Program the INT_LINE register in this device's |
| 195 | * PCI config space with the IRQ number we found in step 3 |
| 196 | * and make it Level Triggered |
| 197 | */ |
| 198 | pci_write_config8(dev, PCI_INTERRUPT_LINE, int_line); |
| 199 | |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame^] | 200 | /* Set IRQ to level triggered since used by a PCI device */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 201 | i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED); |
| 202 | |
| 203 | /* |
| 204 | * Step 5: Print out debug info and move on to next device |
| 205 | */ |
| 206 | printk(BIOS_SPEW, "\tOrig INT_PIN\t: %d (%s)\n", |
| 207 | int_pin, pin_to_str(int_pin)); |
| 208 | if (bridged_device) |
| 209 | printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n", |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame^] | 210 | target_pin, pin_to_str(target_pin)); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 211 | printk(BIOS_SPEW, "\tPCI_INTR idx\t: 0x%02x (%s)\n" |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame^] | 212 | "\tINT_LINE\t: 0x%X (IRQ %d)\n", |
| 213 | pci_intr_idx, intr_types[pci_intr_idx], |
| 214 | int_line, int_line); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 215 | } /* for (dev = all_devices) */ |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame^] | 216 | printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space" |
| 217 | " IRQ assignments\n"); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 218 | } |