Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 3 | |
| 4 | #include <console/console.h> |
| 5 | #include <device/pci.h> |
| 6 | #include <arch/io.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 7 | #include <device/pci_ops.h> |
Richard Spiegel | 2bbc3dc | 2017-12-06 16:14:58 -0700 | [diff] [blame] | 8 | #include <amdblocks/amd_pci_util.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 9 | #include <pc80/i8259.h> |
Richard Spiegel | a800bdb | 2017-11-13 16:59:38 -0700 | [diff] [blame] | 10 | #include <soc/amd_pci_int_defs.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 11 | |
Aaron Durbin | 8dd4006 | 2017-11-03 11:50:14 -0600 | [diff] [blame] | 12 | const struct pirq_struct *pirq_data_ptr; |
| 13 | u32 pirq_data_size; |
| 14 | const u8 *intr_data_ptr; |
| 15 | const u8 *picr_data_ptr; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 16 | |
| 17 | /* |
| 18 | * Read the FCH PCI_INTR registers 0xC00/0xC01 at a |
| 19 | * given index and a given PIC (0) or IOAPIC (1) mode |
| 20 | */ |
| 21 | u8 read_pci_int_idx(u8 index, int mode) |
| 22 | { |
| 23 | outb((mode << 7) | index, PCI_INTR_INDEX); |
| 24 | return inb(PCI_INTR_DATA); |
| 25 | } |
| 26 | |
| 27 | /* |
| 28 | * Write a value to the FCH PCI_INTR registers 0xC00/0xC01 |
| 29 | * at a given index and PIC (0) or IOAPIC (1) mode |
| 30 | */ |
| 31 | void write_pci_int_idx(u8 index, int mode, u8 data) |
| 32 | { |
| 33 | outb((mode << 7) | index, PCI_INTR_INDEX); |
| 34 | outb(data, PCI_INTR_DATA); |
| 35 | } |
| 36 | |
| 37 | /* |
| 38 | * Write the FCH PCI_INTR registers 0xC00/0xC01 with values |
| 39 | * given in global variables intr_data and picr_data. |
| 40 | * These variables are defined in mainboard.c |
| 41 | */ |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 42 | void write_pci_int_table(void) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 43 | { |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 44 | uint8_t byte; |
| 45 | size_t i, limit; |
| 46 | const struct irq_idx_name *idx_name; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 47 | |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 48 | idx_name = sb_get_apic_reg_association(&limit); |
Richard Spiegel | 6c2ab06 | 2017-12-18 09:52:42 -0700 | [diff] [blame] | 49 | if (picr_data_ptr == NULL || intr_data_ptr == NULL || |
| 50 | idx_name == NULL) { |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 51 | printk(BIOS_ERR, "Warning: Can't write PCI_INTR 0xC00/0xC01" |
| 52 | " registers because\n" |
Richard Spiegel | 6c2ab06 | 2017-12-18 09:52:42 -0700 | [diff] [blame] | 53 | "'mainboard_picr_data' or 'mainboard_intr_data'" |
| 54 | " or 'irq_association'\ntables are NULL\n"); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 55 | return; |
| 56 | } |
| 57 | |
| 58 | /* PIC IRQ routine */ |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 59 | printk(BIOS_DEBUG, "PCI_INTR tables: Writing registers C00/C01 for" |
| 60 | " PCI IRQ routing:\n" |
Richard Spiegel | e89d444 | 2017-12-08 07:52:42 -0700 | [diff] [blame] | 61 | "PCI_INTR_INDEX\tname\t\t PIC mode" |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 62 | "\tAPIC mode\n"); |
| 63 | /* |
| 64 | * Iterate table idx_name, indexes outside the table are ignored |
| 65 | * (assumed not connected within the chip). For each iteration, |
| 66 | * get the register index "byte" and the name of the associated |
| 67 | * IRQ source for printing. |
| 68 | */ |
| 69 | for (i = 0 ; i < limit; i++) { |
| 70 | byte = idx_name[i].index; |
| 71 | write_pci_int_idx(byte, 0, (u8) picr_data_ptr[byte]); |
Richard Spiegel | e89d444 | 2017-12-08 07:52:42 -0700 | [diff] [blame] | 72 | printk(BIOS_DEBUG, "0x%02X\t\t%-20s 0x%02X\t", |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 73 | byte, idx_name[i].name, |
| 74 | read_pci_int_idx(byte, 0)); |
| 75 | write_pci_int_idx(byte, 1, (u8) intr_data_ptr[byte]); |
| 76 | printk(BIOS_DEBUG, "0x%02X\n", read_pci_int_idx(byte, 1)); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 77 | } |
| 78 | } |
| 79 | |
| 80 | /* |
| 81 | * Function to write the PCI config space Interrupt |
| 82 | * registers based on the values given in PCI_INTR |
| 83 | * table at I/O port 0xC00/0xC01 |
| 84 | */ |
| 85 | void write_pci_cfg_irqs(void) |
| 86 | { |
Elyes HAOUAS | 0f5957a | 2018-05-22 10:58:50 +0200 | [diff] [blame] | 87 | struct device *dev = NULL; /* Our current device to route IRQs */ |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 88 | struct device *target_dev = NULL; /* the bridge a device may be |
| 89 | * connected to */ |
| 90 | u16 int_pin = 0; |
| 91 | u16 target_pin = 0; |
| 92 | u16 int_line = 0; |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 93 | u16 pci_intr_idx = 0; /* Index into PCI_INTR table, 0xC00/0xC01 */ |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 94 | u16 devfn = 0; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 95 | u32 i = 0; |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 96 | size_t limit; |
| 97 | const struct irq_idx_name *idx_name; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 98 | |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 99 | idx_name = sb_get_apic_reg_association(&limit); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 100 | if (pirq_data_ptr == NULL) { |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 101 | printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments" |
| 102 | " because 'mainboard_pirq_data' structure does" |
| 103 | " not exist\n"); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 104 | return; |
| 105 | } |
| 106 | |
| 107 | /* Populate the PCI cfg space header with the IRQ assignment */ |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 108 | printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ" |
| 109 | " assignments\n"); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 110 | |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 111 | for (dev = all_devices ; dev ; dev = dev->next) { |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 112 | /* |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 113 | * Step 1: Get INT_PIN and device structure to look for in the |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 114 | * PCI_INTR table pirq_data |
| 115 | */ |
| 116 | target_dev = NULL; |
| 117 | target_pin = get_pci_irq_pins(dev, &target_dev); |
| 118 | if (target_dev == NULL) |
| 119 | continue; |
| 120 | |
| 121 | if (target_pin < 1) |
| 122 | continue; |
| 123 | |
| 124 | /* Get the original INT_PIN for record keeping */ |
| 125 | int_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN); |
| 126 | if (int_pin < 1 || int_pin > 4) |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 127 | continue; /* Device has invalid INT_PIN - skip */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 128 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 129 | devfn = target_dev->path.pci.devfn; |
| 130 | |
| 131 | /* |
| 132 | * Step 2: Use the INT_PIN and DevFn number to find the PCI_INTR |
| 133 | * register (0xC00) index for this device |
| 134 | */ |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 135 | pci_intr_idx = 0xbad; /* Will check to make sure it changed */ |
| 136 | for (i = 0 ; i < pirq_data_size ; i++) { |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 137 | if (pirq_data_ptr[i].devfn != devfn) |
| 138 | continue; |
| 139 | |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 140 | /* PIN_A is idx0 in pirq_data array but 1 in PCI reg */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 141 | pci_intr_idx = pirq_data_ptr[i].PIN[target_pin - 1]; |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 142 | printk(BIOS_SPEW, "\tFound this device in pirq_data" |
| 143 | " table entry %d\n", i); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 144 | break; |
| 145 | } |
| 146 | |
| 147 | /* |
| 148 | * Step 3: Make sure we got a valid index and use it to get |
| 149 | * the IRQ number from the PCI_INTR register table |
| 150 | */ |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 151 | if (pci_intr_idx == 0xbad) { |
| 152 | /* Not on a bridge or in pirq_data table, skip it */ |
| 153 | printk(BIOS_SPEW, "PCI Devfn (0x%x) not found in" |
| 154 | " pirq_data table\n", devfn); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 155 | continue; |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 156 | } else if (pci_intr_idx == 0x1f) { |
| 157 | /* Index found is not defined */ |
| 158 | printk(BIOS_SPEW, "Got index 0x1F (Not Connected)," |
| 159 | " perhaps this device was" |
| 160 | " defined wrong?\n"); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 161 | continue; |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 162 | } |
| 163 | /* |
| 164 | * Find the name associated with register [pci_intr_idx] |
| 165 | * and print information. |
| 166 | */ |
| 167 | for (i = 0; i < limit; i++) { |
| 168 | if (idx_name[i].index == pci_intr_idx) |
| 169 | break; |
| 170 | } |
| 171 | if (i == limit) { |
| 172 | printk(BIOS_SPEW, "Got register index 0x%02x" |
| 173 | " undefined in table irq_idx_name,\n" |
| 174 | " perhaps this device was" |
| 175 | " defined wrong?\n", pci_intr_idx); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 176 | continue; |
| 177 | } |
| 178 | |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 179 | /* Find the value to program into the INT_LINE register from |
| 180 | * the PCI_INTR registers |
| 181 | */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 182 | int_line = read_pci_int_idx(pci_intr_idx, 0); |
| 183 | if (int_line == PIRQ_NC) { /* The IRQ found is disabled */ |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 184 | printk(BIOS_SPEW, "Got IRQ 0x1F (disabled), perhaps" |
| 185 | " this device was defined wrong?\n"); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 186 | continue; |
| 187 | } |
| 188 | |
| 189 | /* |
| 190 | * Step 4: Program the INT_LINE register in this device's |
| 191 | * PCI config space with the IRQ number we found in step 3 |
| 192 | * and make it Level Triggered |
| 193 | */ |
| 194 | pci_write_config8(dev, PCI_INTERRUPT_LINE, int_line); |
| 195 | |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 196 | /* Set IRQ to level triggered since used by a PCI device */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 197 | i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED); |
| 198 | |
| 199 | /* |
| 200 | * Step 5: Print out debug info and move on to next device |
| 201 | */ |
| 202 | printk(BIOS_SPEW, "\tOrig INT_PIN\t: %d (%s)\n", |
| 203 | int_pin, pin_to_str(int_pin)); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 204 | printk(BIOS_SPEW, "\tPCI_INTR idx\t: 0x%02x (%s)\n" |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 205 | "\tINT_LINE\t: 0x%X (IRQ %d)\n", |
| 206 | pci_intr_idx, idx_name[i].name, |
| 207 | int_line, int_line); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 208 | } /* for (dev = all_devices) */ |
Marshall Dawson | f3dc71e | 2017-06-14 16:22:07 -0600 | [diff] [blame] | 209 | printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space" |
| 210 | " IRQ assignments\n"); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 211 | } |