Angel Pons | 0612b27 | 2020-04-05 15:46:56 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 2 | |
John Zhao | 41aa8d6 | 2022-01-20 11:29:18 -0800 | [diff] [blame^] | 3 | #define __SIMPLE_DEVICE__ |
| 4 | |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 5 | #include <device/pci_ops.h> |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 6 | #include <console/console.h> |
| 7 | #include <device/device.h> |
| 8 | #include <device/pci.h> |
| 9 | #include <device/pci_ids.h> |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 10 | #include <intelblocks/p2sb.h> |
John Zhao | 41aa8d6 | 2022-01-20 11:29:18 -0800 | [diff] [blame^] | 11 | #include <intelblocks/p2sblib.h> |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 12 | #include <soc/iomap.h> |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 13 | #include <soc/p2sb.h> |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 14 | #include <soc/pci_devs.h> |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 15 | #include <string.h> |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 16 | |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 17 | #define PCH_P2SB_EPMASK(mask_number) (PCH_P2SB_EPMASK0 + ((mask_number) * 4)) |
| 18 | |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 19 | void p2sb_enable_bar(void) |
| 20 | { |
| 21 | /* Enable PCR Base address in PCH */ |
Nico Huber | e549503 | 2020-02-17 18:26:51 +0100 | [diff] [blame] | 22 | pci_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, P2SB_BAR); |
| 23 | pci_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_1, 0); |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 24 | |
| 25 | /* Enable P2SB MSE */ |
Elyes HAOUAS | 2ec1c13 | 2020-04-29 09:57:05 +0200 | [diff] [blame] | 26 | pci_write_config16(PCH_DEV_P2SB, PCI_COMMAND, |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 27 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); |
| 28 | } |
| 29 | |
| 30 | /* |
| 31 | * Enable decoding for HPET range. |
| 32 | * This is needed for FspMemoryInit to store and retrieve a global data |
| 33 | * pointer. |
| 34 | */ |
| 35 | void p2sb_configure_hpet(void) |
| 36 | { |
| 37 | /* |
| 38 | * Enable decoding for HPET memory address range. |
| 39 | * HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode |
| 40 | * the High Performance Timer memory address range |
| 41 | * selected by bits 1:0 |
| 42 | */ |
Nico Huber | e549503 | 2020-02-17 18:26:51 +0100 | [diff] [blame] | 43 | pci_write_config8(PCH_DEV_P2SB, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT); |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 44 | } |
| 45 | |
Arthur Heymans | f629f7b | 2020-11-12 21:00:03 +0100 | [diff] [blame] | 46 | union p2sb_bdf p2sb_get_hpet_bdf(void) |
| 47 | { |
John Zhao | 41aa8d6 | 2022-01-20 11:29:18 -0800 | [diff] [blame^] | 48 | const bool was_hidden = p2sb_dev_is_hidden(PCH_DEV_P2SB); |
Arthur Heymans | f629f7b | 2020-11-12 21:00:03 +0100 | [diff] [blame] | 49 | if (was_hidden) |
| 50 | p2sb_unhide(); |
| 51 | |
| 52 | union p2sb_bdf bdf = { .raw = pci_read_config16(PCH_DEV_P2SB, PCH_P2SB_HBDF) }; |
| 53 | |
| 54 | if (was_hidden) |
| 55 | p2sb_hide(); |
| 56 | |
| 57 | return bdf; |
| 58 | } |
| 59 | |
| 60 | void p2sb_set_hpet_bdf(union p2sb_bdf bdf) |
| 61 | { |
| 62 | pci_write_config16(PCH_DEV_P2SB, PCH_P2SB_HBDF, bdf.raw); |
| 63 | } |
| 64 | |
Arthur Heymans | a1f65be | 2020-11-12 21:07:13 +0100 | [diff] [blame] | 65 | union p2sb_bdf p2sb_get_ioapic_bdf(void) |
| 66 | { |
John Zhao | 41aa8d6 | 2022-01-20 11:29:18 -0800 | [diff] [blame^] | 67 | const bool was_hidden = p2sb_dev_is_hidden(PCH_DEV_P2SB); |
Arthur Heymans | a1f65be | 2020-11-12 21:07:13 +0100 | [diff] [blame] | 68 | if (was_hidden) |
| 69 | p2sb_unhide(); |
| 70 | |
| 71 | union p2sb_bdf bdf = { .raw = pci_read_config16(PCH_DEV_P2SB, PCH_P2SB_IBDF) }; |
| 72 | |
| 73 | if (was_hidden) |
| 74 | p2sb_hide(); |
| 75 | |
| 76 | return bdf; |
| 77 | } |
| 78 | |
| 79 | void p2sb_set_ioapic_bdf(union p2sb_bdf bdf) |
| 80 | { |
| 81 | pci_write_config16(PCH_DEV_P2SB, PCH_P2SB_IBDF, bdf.raw); |
| 82 | } |
| 83 | |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 84 | void p2sb_unhide(void) |
| 85 | { |
John Zhao | 41aa8d6 | 2022-01-20 11:29:18 -0800 | [diff] [blame^] | 86 | p2sb_dev_unhide(PCH_DEV_P2SB); |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 87 | } |
| 88 | |
| 89 | void p2sb_hide(void) |
| 90 | { |
John Zhao | 41aa8d6 | 2022-01-20 11:29:18 -0800 | [diff] [blame^] | 91 | p2sb_dev_hide(PCH_DEV_P2SB); |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 92 | } |
| 93 | |
| 94 | static void p2sb_configure_endpoints(int epmask_id, uint32_t mask) |
| 95 | { |
| 96 | uint32_t reg32; |
| 97 | |
Nico Huber | e549503 | 2020-02-17 18:26:51 +0100 | [diff] [blame] | 98 | reg32 = pci_read_config32(PCH_DEV_P2SB, PCH_P2SB_EPMASK(epmask_id)); |
| 99 | pci_write_config32(PCH_DEV_P2SB, PCH_P2SB_EPMASK(epmask_id), |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 100 | reg32 | mask); |
| 101 | } |
| 102 | |
| 103 | static void p2sb_lock_endpoints(void) |
| 104 | { |
| 105 | uint8_t reg8; |
| 106 | |
| 107 | /* Set the "Endpoint Mask Lock!", P2SB PCI offset E2h bit[1] to 1. */ |
Nico Huber | e549503 | 2020-02-17 18:26:51 +0100 | [diff] [blame] | 108 | reg8 = pci_read_config8(PCH_DEV_P2SB, PCH_P2SB_E0 + 2); |
| 109 | pci_write_config8(PCH_DEV_P2SB, PCH_P2SB_E0 + 2, |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 110 | reg8 | P2SB_E0_MASKLOCK); |
| 111 | } |
| 112 | |
| 113 | void p2sb_disable_sideband_access(void) |
| 114 | { |
| 115 | uint32_t ep_mask[P2SB_EP_MASK_MAX_REG]; |
| 116 | int i; |
| 117 | |
| 118 | memset(ep_mask, 0, sizeof(ep_mask)); |
| 119 | |
| 120 | p2sb_soc_get_sb_mask(ep_mask, ARRAY_SIZE(ep_mask)); |
| 121 | |
| 122 | /* Remove the host accessing right to PSF register range. */ |
| 123 | for (i = 0; i < P2SB_EP_MASK_MAX_REG; i++) |
| 124 | p2sb_configure_endpoints(i, ep_mask[i]); |
| 125 | |
| 126 | p2sb_lock_endpoints(); |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 127 | } |
| 128 | |
| 129 | static void read_resources(struct device *dev) |
| 130 | { |
| 131 | /* |
| 132 | * There's only one resource on the P2SB device. It's also already |
| 133 | * manually set to a fixed address in earlier boot stages. |
Patrick Rudolph | 8d7a89b | 2019-10-04 09:22:27 +0200 | [diff] [blame] | 134 | * The following code makes sure that it doesn't change if the device |
| 135 | * is visible and the resource allocator is being run. |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 136 | */ |
| 137 | mmio_resource(dev, PCI_BASE_ADDRESS_0, P2SB_BAR / KiB, P2SB_SIZE / KiB); |
| 138 | } |
| 139 | |
| 140 | static const struct device_operations device_ops = { |
| 141 | .read_resources = read_resources, |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame] | 142 | .set_resources = noop_set_resources, |
Subrata Banik | 6bbc91a | 2017-12-07 14:55:51 +0530 | [diff] [blame] | 143 | .ops_pci = &pci_dev_ops_pci, |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 144 | }; |
| 145 | |
| 146 | static const unsigned short pci_device_ids[] = { |
| 147 | PCI_DEVICE_ID_INTEL_APL_P2SB, |
| 148 | PCI_DEVICE_ID_INTEL_GLK_P2SB, |
Maxim Polyakov | 571d07d | 2019-08-22 13:11:32 +0300 | [diff] [blame] | 149 | PCI_DEVICE_ID_INTEL_LWB_P2SB, |
| 150 | PCI_DEVICE_ID_INTEL_LWB_P2SB_SUPER, |
Patrick Rudolph | 8d7a89b | 2019-10-04 09:22:27 +0200 | [diff] [blame] | 151 | PCI_DEVICE_ID_INTEL_SKL_LP_P2SB, |
| 152 | PCI_DEVICE_ID_INTEL_SKL_P2SB, |
| 153 | PCI_DEVICE_ID_INTEL_KBL_P2SB, |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 154 | PCI_DEVICE_ID_INTEL_CNL_P2SB, |
praveen hodagatta pranesh | e26c4a4 | 2018-09-20 03:49:45 +0800 | [diff] [blame] | 155 | PCI_DEVICE_ID_INTEL_CNP_H_P2SB, |
Aamir Bohra | 9eac039 | 2018-06-30 12:07:04 +0530 | [diff] [blame] | 156 | PCI_DEVICE_ID_INTEL_ICL_P2SB, |
Ronak Kanabar | da7ffb48 | 2019-02-05 01:51:13 +0530 | [diff] [blame] | 157 | PCI_DEVICE_ID_INTEL_CMP_P2SB, |
Gaggery Tsai | 12a651c | 2019-12-05 11:23:20 -0800 | [diff] [blame] | 158 | PCI_DEVICE_ID_INTEL_CMP_H_P2SB, |
Ravi Sarawadi | 6b5bf40 | 2019-10-21 22:25:04 -0700 | [diff] [blame] | 159 | PCI_DEVICE_ID_INTEL_TGL_P2SB, |
Jeremy Soller | 191a8d7 | 2021-08-10 14:06:51 -0600 | [diff] [blame] | 160 | PCI_DEVICE_ID_INTEL_TGL_H_P2SB, |
Tan, Lean Sheng | 2613609 | 2020-01-20 19:13:56 -0800 | [diff] [blame] | 161 | PCI_DEVICE_ID_INTEL_EHL_P2SB, |
Meera Ravindranath | 3f4af0d | 2020-02-12 16:01:22 +0530 | [diff] [blame] | 162 | PCI_DEVICE_ID_INTEL_JSP_P2SB, |
Subrata Banik | f672f7f | 2020-08-03 14:29:25 +0530 | [diff] [blame] | 163 | PCI_DEVICE_ID_INTEL_ADP_P_P2SB, |
| 164 | PCI_DEVICE_ID_INTEL_ADP_S_P2SB, |
Varshit Pandya | f4d98fdd2 | 2021-01-17 18:39:29 +0530 | [diff] [blame] | 165 | PCI_DEVICE_ID_INTEL_ADP_M_P2SB, |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 166 | 0, |
| 167 | }; |
| 168 | |
| 169 | static const struct pci_driver pmc __pci_driver = { |
| 170 | .ops = &device_ops, |
| 171 | .vendor = PCI_VENDOR_ID_INTEL, |
| 172 | .devices = pci_device_ids, |
| 173 | }; |