Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 4 | * Copyright (C) 2016 Google Inc. |
| 5 | * Copyright (C) 2018 Intel Corporation. |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <arch/io.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame^] | 18 | #include <device/pci_ops.h> |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 19 | #include <console/console.h> |
| 20 | #include <device/device.h> |
| 21 | #include <device/pci.h> |
| 22 | #include <device/pci_ids.h> |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 23 | #include <intelblocks/p2sb.h> |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 24 | #include <soc/iomap.h> |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 25 | #include <soc/p2sb.h> |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 26 | #include <soc/pci_devs.h> |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 27 | #include <string.h> |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 28 | |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 29 | #define PCH_P2SB_EPMASK(mask_number) (PCH_P2SB_EPMASK0 + ((mask_number) * 4)) |
| 30 | |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 31 | #define HIDE_BIT (1 << 0) |
| 32 | |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 33 | #if defined(__SIMPLE_DEVICE__) |
| 34 | static pci_devfn_t p2sb_get_device(void) |
| 35 | { |
| 36 | int devfn = PCH_DEVFN_P2SB; |
| 37 | pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); |
| 38 | |
| 39 | if (dev == PCI_DEV_INVALID) |
| 40 | die("PCH_DEV_P2SB not found!\n"); |
| 41 | |
| 42 | return dev; |
| 43 | } |
| 44 | #else |
| 45 | static struct device *p2sb_get_device(void) |
| 46 | { |
| 47 | struct device *dev = PCH_DEV_P2SB; |
| 48 | if (!dev) |
| 49 | die("PCH_DEV_P2SB not found!\n"); |
| 50 | |
| 51 | return dev; |
| 52 | } |
| 53 | #endif |
| 54 | |
| 55 | #define P2SB_GET_DEV p2sb_get_device() |
| 56 | |
| 57 | void p2sb_enable_bar(void) |
| 58 | { |
| 59 | /* Enable PCR Base address in PCH */ |
| 60 | pci_write_config32(P2SB_GET_DEV, PCI_BASE_ADDRESS_0, P2SB_BAR); |
| 61 | pci_write_config32(P2SB_GET_DEV, PCI_BASE_ADDRESS_1, 0); |
| 62 | |
| 63 | /* Enable P2SB MSE */ |
| 64 | pci_write_config8(P2SB_GET_DEV, PCI_COMMAND, |
| 65 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); |
| 66 | } |
| 67 | |
| 68 | /* |
| 69 | * Enable decoding for HPET range. |
| 70 | * This is needed for FspMemoryInit to store and retrieve a global data |
| 71 | * pointer. |
| 72 | */ |
| 73 | void p2sb_configure_hpet(void) |
| 74 | { |
| 75 | /* |
| 76 | * Enable decoding for HPET memory address range. |
| 77 | * HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode |
| 78 | * the High Performance Timer memory address range |
| 79 | * selected by bits 1:0 |
| 80 | */ |
| 81 | pci_write_config8(P2SB_GET_DEV, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT); |
| 82 | } |
| 83 | |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 84 | static void p2sb_set_hide_bit(int hide) |
| 85 | { |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 86 | const uint16_t reg = PCH_P2SB_E0 + 1; |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 87 | const uint8_t mask = HIDE_BIT; |
| 88 | uint8_t val; |
| 89 | |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 90 | val = pci_read_config8(P2SB_GET_DEV, reg); |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 91 | val &= ~mask; |
| 92 | if (hide) |
| 93 | val |= mask; |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 94 | pci_write_config8(P2SB_GET_DEV, reg, val); |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 95 | } |
| 96 | |
| 97 | void p2sb_unhide(void) |
| 98 | { |
| 99 | p2sb_set_hide_bit(0); |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 100 | |
| 101 | if (pci_read_config16(P2SB_GET_DEV, PCI_VENDOR_ID) != |
| 102 | PCI_VENDOR_ID_INTEL) |
| 103 | die("Unable to unhide PCH_DEV_P2SB device !\n"); |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 104 | } |
| 105 | |
| 106 | void p2sb_hide(void) |
| 107 | { |
| 108 | p2sb_set_hide_bit(1); |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 109 | |
| 110 | if (pci_read_config16(P2SB_GET_DEV, PCI_VENDOR_ID) != |
| 111 | 0xFFFF) |
| 112 | die("Unable to hide PCH_DEV_P2SB device !\n"); |
| 113 | } |
| 114 | |
| 115 | static void p2sb_configure_endpoints(int epmask_id, uint32_t mask) |
| 116 | { |
| 117 | uint32_t reg32; |
| 118 | |
| 119 | reg32 = pci_read_config32(P2SB_GET_DEV, PCH_P2SB_EPMASK(epmask_id)); |
| 120 | pci_write_config32(P2SB_GET_DEV, PCH_P2SB_EPMASK(epmask_id), |
| 121 | reg32 | mask); |
| 122 | } |
| 123 | |
| 124 | static void p2sb_lock_endpoints(void) |
| 125 | { |
| 126 | uint8_t reg8; |
| 127 | |
| 128 | /* Set the "Endpoint Mask Lock!", P2SB PCI offset E2h bit[1] to 1. */ |
| 129 | reg8 = pci_read_config8(P2SB_GET_DEV, PCH_P2SB_E0 + 2); |
| 130 | pci_write_config8(P2SB_GET_DEV, PCH_P2SB_E0 + 2, |
| 131 | reg8 | P2SB_E0_MASKLOCK); |
| 132 | } |
| 133 | |
| 134 | void p2sb_disable_sideband_access(void) |
| 135 | { |
| 136 | uint32_t ep_mask[P2SB_EP_MASK_MAX_REG]; |
| 137 | int i; |
| 138 | |
| 139 | memset(ep_mask, 0, sizeof(ep_mask)); |
| 140 | |
| 141 | p2sb_soc_get_sb_mask(ep_mask, ARRAY_SIZE(ep_mask)); |
| 142 | |
| 143 | /* Remove the host accessing right to PSF register range. */ |
| 144 | for (i = 0; i < P2SB_EP_MASK_MAX_REG; i++) |
| 145 | p2sb_configure_endpoints(i, ep_mask[i]); |
| 146 | |
| 147 | p2sb_lock_endpoints(); |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 148 | } |
| 149 | |
| 150 | static void read_resources(struct device *dev) |
| 151 | { |
| 152 | /* |
| 153 | * There's only one resource on the P2SB device. It's also already |
| 154 | * manually set to a fixed address in earlier boot stages. |
| 155 | */ |
| 156 | mmio_resource(dev, PCI_BASE_ADDRESS_0, P2SB_BAR / KiB, P2SB_SIZE / KiB); |
| 157 | } |
| 158 | |
| 159 | static const struct device_operations device_ops = { |
| 160 | .read_resources = read_resources, |
| 161 | .set_resources = DEVICE_NOOP, |
Subrata Banik | 6bbc91a | 2017-12-07 14:55:51 +0530 | [diff] [blame] | 162 | .ops_pci = &pci_dev_ops_pci, |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 163 | }; |
| 164 | |
| 165 | static const unsigned short pci_device_ids[] = { |
| 166 | PCI_DEVICE_ID_INTEL_APL_P2SB, |
| 167 | PCI_DEVICE_ID_INTEL_GLK_P2SB, |
| 168 | PCI_DEVICE_ID_INTEL_CNL_P2SB, |
praveen hodagatta pranesh | e26c4a4 | 2018-09-20 03:49:45 +0800 | [diff] [blame] | 169 | PCI_DEVICE_ID_INTEL_CNP_H_P2SB, |
Aamir Bohra | 9eac039 | 2018-06-30 12:07:04 +0530 | [diff] [blame] | 170 | PCI_DEVICE_ID_INTEL_ICL_P2SB, |
Ronak Kanabar | da7ffb48 | 2019-02-05 01:51:13 +0530 | [diff] [blame] | 171 | PCI_DEVICE_ID_INTEL_CMP_P2SB, |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 172 | 0, |
| 173 | }; |
| 174 | |
| 175 | static const struct pci_driver pmc __pci_driver = { |
| 176 | .ops = &device_ops, |
| 177 | .vendor = PCI_VENDOR_ID_INTEL, |
| 178 | .devices = pci_device_ids, |
| 179 | }; |