Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 4 | * Copyright (C) 2016 Google Inc. |
| 5 | * Copyright (C) 2018 Intel Corporation. |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 17 | #include <device/pci_ops.h> |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 18 | #include <console/console.h> |
| 19 | #include <device/device.h> |
| 20 | #include <device/pci.h> |
| 21 | #include <device/pci_ids.h> |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 22 | #include <intelblocks/p2sb.h> |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 23 | #include <soc/iomap.h> |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 24 | #include <soc/p2sb.h> |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 25 | #include <soc/pci_devs.h> |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 26 | #include <string.h> |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 27 | |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 28 | #define PCH_P2SB_EPMASK(mask_number) (PCH_P2SB_EPMASK0 + ((mask_number) * 4)) |
| 29 | |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 30 | #define HIDE_BIT (1 << 0) |
| 31 | |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 32 | void p2sb_enable_bar(void) |
| 33 | { |
| 34 | /* Enable PCR Base address in PCH */ |
Nico Huber | e549503 | 2020-02-17 18:26:51 +0100 | [diff] [blame] | 35 | pci_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, P2SB_BAR); |
| 36 | pci_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_1, 0); |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 37 | |
| 38 | /* Enable P2SB MSE */ |
Nico Huber | e549503 | 2020-02-17 18:26:51 +0100 | [diff] [blame] | 39 | pci_write_config8(PCH_DEV_P2SB, PCI_COMMAND, |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 40 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); |
| 41 | } |
| 42 | |
| 43 | /* |
| 44 | * Enable decoding for HPET range. |
| 45 | * This is needed for FspMemoryInit to store and retrieve a global data |
| 46 | * pointer. |
| 47 | */ |
| 48 | void p2sb_configure_hpet(void) |
| 49 | { |
| 50 | /* |
| 51 | * Enable decoding for HPET memory address range. |
| 52 | * HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode |
| 53 | * the High Performance Timer memory address range |
| 54 | * selected by bits 1:0 |
| 55 | */ |
Nico Huber | e549503 | 2020-02-17 18:26:51 +0100 | [diff] [blame] | 56 | pci_write_config8(PCH_DEV_P2SB, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT); |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 57 | } |
| 58 | |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 59 | static void p2sb_set_hide_bit(int hide) |
| 60 | { |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 61 | const uint16_t reg = PCH_P2SB_E0 + 1; |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 62 | const uint8_t mask = HIDE_BIT; |
| 63 | uint8_t val; |
| 64 | |
Nico Huber | e549503 | 2020-02-17 18:26:51 +0100 | [diff] [blame] | 65 | val = pci_read_config8(PCH_DEV_P2SB, reg); |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 66 | val &= ~mask; |
| 67 | if (hide) |
| 68 | val |= mask; |
Nico Huber | e549503 | 2020-02-17 18:26:51 +0100 | [diff] [blame] | 69 | pci_write_config8(PCH_DEV_P2SB, reg, val); |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 70 | } |
| 71 | |
| 72 | void p2sb_unhide(void) |
| 73 | { |
| 74 | p2sb_set_hide_bit(0); |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 75 | |
Nico Huber | e549503 | 2020-02-17 18:26:51 +0100 | [diff] [blame] | 76 | if (pci_read_config16(PCH_DEV_P2SB, PCI_VENDOR_ID) != |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 77 | PCI_VENDOR_ID_INTEL) |
Keith Short | 15588b0 | 2019-05-09 11:40:34 -0600 | [diff] [blame] | 78 | die_with_post_code(POST_HW_INIT_FAILURE, |
| 79 | "Unable to unhide PCH_DEV_P2SB device !\n"); |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 80 | } |
| 81 | |
| 82 | void p2sb_hide(void) |
| 83 | { |
| 84 | p2sb_set_hide_bit(1); |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 85 | |
Nico Huber | e549503 | 2020-02-17 18:26:51 +0100 | [diff] [blame] | 86 | if (pci_read_config16(PCH_DEV_P2SB, PCI_VENDOR_ID) != |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 87 | 0xFFFF) |
Keith Short | 15588b0 | 2019-05-09 11:40:34 -0600 | [diff] [blame] | 88 | die_with_post_code(POST_HW_INIT_FAILURE, |
| 89 | "Unable to hide PCH_DEV_P2SB device !\n"); |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 90 | } |
| 91 | |
| 92 | static void p2sb_configure_endpoints(int epmask_id, uint32_t mask) |
| 93 | { |
| 94 | uint32_t reg32; |
| 95 | |
Nico Huber | e549503 | 2020-02-17 18:26:51 +0100 | [diff] [blame] | 96 | reg32 = pci_read_config32(PCH_DEV_P2SB, PCH_P2SB_EPMASK(epmask_id)); |
| 97 | pci_write_config32(PCH_DEV_P2SB, PCH_P2SB_EPMASK(epmask_id), |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 98 | reg32 | mask); |
| 99 | } |
| 100 | |
| 101 | static void p2sb_lock_endpoints(void) |
| 102 | { |
| 103 | uint8_t reg8; |
| 104 | |
| 105 | /* Set the "Endpoint Mask Lock!", P2SB PCI offset E2h bit[1] to 1. */ |
Nico Huber | e549503 | 2020-02-17 18:26:51 +0100 | [diff] [blame] | 106 | reg8 = pci_read_config8(PCH_DEV_P2SB, PCH_P2SB_E0 + 2); |
| 107 | pci_write_config8(PCH_DEV_P2SB, PCH_P2SB_E0 + 2, |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 108 | reg8 | P2SB_E0_MASKLOCK); |
| 109 | } |
| 110 | |
| 111 | void p2sb_disable_sideband_access(void) |
| 112 | { |
| 113 | uint32_t ep_mask[P2SB_EP_MASK_MAX_REG]; |
| 114 | int i; |
| 115 | |
| 116 | memset(ep_mask, 0, sizeof(ep_mask)); |
| 117 | |
| 118 | p2sb_soc_get_sb_mask(ep_mask, ARRAY_SIZE(ep_mask)); |
| 119 | |
| 120 | /* Remove the host accessing right to PSF register range. */ |
| 121 | for (i = 0; i < P2SB_EP_MASK_MAX_REG; i++) |
| 122 | p2sb_configure_endpoints(i, ep_mask[i]); |
| 123 | |
| 124 | p2sb_lock_endpoints(); |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 125 | } |
| 126 | |
| 127 | static void read_resources(struct device *dev) |
| 128 | { |
| 129 | /* |
| 130 | * There's only one resource on the P2SB device. It's also already |
| 131 | * manually set to a fixed address in earlier boot stages. |
Patrick Rudolph | 8d7a89b | 2019-10-04 09:22:27 +0200 | [diff] [blame] | 132 | * The following code makes sure that it doesn't change if the device |
| 133 | * is visible and the resource allocator is being run. |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 134 | */ |
| 135 | mmio_resource(dev, PCI_BASE_ADDRESS_0, P2SB_BAR / KiB, P2SB_SIZE / KiB); |
| 136 | } |
| 137 | |
| 138 | static const struct device_operations device_ops = { |
| 139 | .read_resources = read_resources, |
| 140 | .set_resources = DEVICE_NOOP, |
Subrata Banik | 6bbc91a | 2017-12-07 14:55:51 +0530 | [diff] [blame] | 141 | .ops_pci = &pci_dev_ops_pci, |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 142 | }; |
| 143 | |
| 144 | static const unsigned short pci_device_ids[] = { |
| 145 | PCI_DEVICE_ID_INTEL_APL_P2SB, |
| 146 | PCI_DEVICE_ID_INTEL_GLK_P2SB, |
Maxim Polyakov | 571d07d | 2019-08-22 13:11:32 +0300 | [diff] [blame] | 147 | PCI_DEVICE_ID_INTEL_LWB_P2SB, |
| 148 | PCI_DEVICE_ID_INTEL_LWB_P2SB_SUPER, |
Patrick Rudolph | 8d7a89b | 2019-10-04 09:22:27 +0200 | [diff] [blame] | 149 | PCI_DEVICE_ID_INTEL_SKL_LP_P2SB, |
| 150 | PCI_DEVICE_ID_INTEL_SKL_P2SB, |
| 151 | PCI_DEVICE_ID_INTEL_KBL_P2SB, |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 152 | PCI_DEVICE_ID_INTEL_CNL_P2SB, |
praveen hodagatta pranesh | e26c4a4 | 2018-09-20 03:49:45 +0800 | [diff] [blame] | 153 | PCI_DEVICE_ID_INTEL_CNP_H_P2SB, |
Aamir Bohra | 9eac039 | 2018-06-30 12:07:04 +0530 | [diff] [blame] | 154 | PCI_DEVICE_ID_INTEL_ICL_P2SB, |
Ronak Kanabar | da7ffb48 | 2019-02-05 01:51:13 +0530 | [diff] [blame] | 155 | PCI_DEVICE_ID_INTEL_CMP_P2SB, |
Gaggery Tsai | 12a651c | 2019-12-05 11:23:20 -0800 | [diff] [blame] | 156 | PCI_DEVICE_ID_INTEL_CMP_H_P2SB, |
Ravi Sarawadi | 6b5bf40 | 2019-10-21 22:25:04 -0700 | [diff] [blame] | 157 | PCI_DEVICE_ID_INTEL_TGL_P2SB, |
Tan, Lean Sheng | 2613609 | 2020-01-20 19:13:56 -0800 | [diff] [blame] | 158 | PCI_DEVICE_ID_INTEL_EHL_P2SB, |
Meera Ravindranath | 3f4af0d | 2020-02-12 16:01:22 +0530 | [diff] [blame^] | 159 | PCI_DEVICE_ID_INTEL_JSP_P2SB, |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 160 | 0, |
| 161 | }; |
| 162 | |
| 163 | static const struct pci_driver pmc __pci_driver = { |
| 164 | .ops = &device_ops, |
| 165 | .vendor = PCI_VENDOR_ID_INTEL, |
| 166 | .devices = pci_device_ids, |
| 167 | }; |