Angel Pons | 0612b27 | 2020-04-05 15:46:56 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 3 | |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 4 | #include <device/pci_ops.h> |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 5 | #include <console/console.h> |
| 6 | #include <device/device.h> |
| 7 | #include <device/pci.h> |
| 8 | #include <device/pci_ids.h> |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 9 | #include <intelblocks/p2sb.h> |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 10 | #include <soc/iomap.h> |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 11 | #include <soc/p2sb.h> |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 12 | #include <soc/pci_devs.h> |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 13 | #include <string.h> |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 14 | |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 15 | #define PCH_P2SB_EPMASK(mask_number) (PCH_P2SB_EPMASK0 + ((mask_number) * 4)) |
| 16 | |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 17 | #define HIDE_BIT (1 << 0) |
| 18 | |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 19 | void p2sb_enable_bar(void) |
| 20 | { |
| 21 | /* Enable PCR Base address in PCH */ |
Nico Huber | e549503 | 2020-02-17 18:26:51 +0100 | [diff] [blame] | 22 | pci_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, P2SB_BAR); |
| 23 | pci_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_1, 0); |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 24 | |
| 25 | /* Enable P2SB MSE */ |
Nico Huber | e549503 | 2020-02-17 18:26:51 +0100 | [diff] [blame] | 26 | pci_write_config8(PCH_DEV_P2SB, PCI_COMMAND, |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 27 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); |
| 28 | } |
| 29 | |
| 30 | /* |
| 31 | * Enable decoding for HPET range. |
| 32 | * This is needed for FspMemoryInit to store and retrieve a global data |
| 33 | * pointer. |
| 34 | */ |
| 35 | void p2sb_configure_hpet(void) |
| 36 | { |
| 37 | /* |
| 38 | * Enable decoding for HPET memory address range. |
| 39 | * HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode |
| 40 | * the High Performance Timer memory address range |
| 41 | * selected by bits 1:0 |
| 42 | */ |
Nico Huber | e549503 | 2020-02-17 18:26:51 +0100 | [diff] [blame] | 43 | pci_write_config8(PCH_DEV_P2SB, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT); |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 44 | } |
| 45 | |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 46 | static void p2sb_set_hide_bit(int hide) |
| 47 | { |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 48 | const uint16_t reg = PCH_P2SB_E0 + 1; |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 49 | const uint8_t mask = HIDE_BIT; |
| 50 | uint8_t val; |
| 51 | |
Nico Huber | e549503 | 2020-02-17 18:26:51 +0100 | [diff] [blame] | 52 | val = pci_read_config8(PCH_DEV_P2SB, reg); |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 53 | val &= ~mask; |
| 54 | if (hide) |
| 55 | val |= mask; |
Nico Huber | e549503 | 2020-02-17 18:26:51 +0100 | [diff] [blame] | 56 | pci_write_config8(PCH_DEV_P2SB, reg, val); |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 57 | } |
| 58 | |
| 59 | void p2sb_unhide(void) |
| 60 | { |
| 61 | p2sb_set_hide_bit(0); |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 62 | |
Nico Huber | e549503 | 2020-02-17 18:26:51 +0100 | [diff] [blame] | 63 | if (pci_read_config16(PCH_DEV_P2SB, PCI_VENDOR_ID) != |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 64 | PCI_VENDOR_ID_INTEL) |
Keith Short | 15588b0 | 2019-05-09 11:40:34 -0600 | [diff] [blame] | 65 | die_with_post_code(POST_HW_INIT_FAILURE, |
| 66 | "Unable to unhide PCH_DEV_P2SB device !\n"); |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 67 | } |
| 68 | |
| 69 | void p2sb_hide(void) |
| 70 | { |
| 71 | p2sb_set_hide_bit(1); |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 72 | |
Nico Huber | e549503 | 2020-02-17 18:26:51 +0100 | [diff] [blame] | 73 | if (pci_read_config16(PCH_DEV_P2SB, PCI_VENDOR_ID) != |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 74 | 0xFFFF) |
Keith Short | 15588b0 | 2019-05-09 11:40:34 -0600 | [diff] [blame] | 75 | die_with_post_code(POST_HW_INIT_FAILURE, |
| 76 | "Unable to hide PCH_DEV_P2SB device !\n"); |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 77 | } |
| 78 | |
| 79 | static void p2sb_configure_endpoints(int epmask_id, uint32_t mask) |
| 80 | { |
| 81 | uint32_t reg32; |
| 82 | |
Nico Huber | e549503 | 2020-02-17 18:26:51 +0100 | [diff] [blame] | 83 | reg32 = pci_read_config32(PCH_DEV_P2SB, PCH_P2SB_EPMASK(epmask_id)); |
| 84 | pci_write_config32(PCH_DEV_P2SB, PCH_P2SB_EPMASK(epmask_id), |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 85 | reg32 | mask); |
| 86 | } |
| 87 | |
| 88 | static void p2sb_lock_endpoints(void) |
| 89 | { |
| 90 | uint8_t reg8; |
| 91 | |
| 92 | /* Set the "Endpoint Mask Lock!", P2SB PCI offset E2h bit[1] to 1. */ |
Nico Huber | e549503 | 2020-02-17 18:26:51 +0100 | [diff] [blame] | 93 | reg8 = pci_read_config8(PCH_DEV_P2SB, PCH_P2SB_E0 + 2); |
| 94 | pci_write_config8(PCH_DEV_P2SB, PCH_P2SB_E0 + 2, |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 95 | reg8 | P2SB_E0_MASKLOCK); |
| 96 | } |
| 97 | |
| 98 | void p2sb_disable_sideband_access(void) |
| 99 | { |
| 100 | uint32_t ep_mask[P2SB_EP_MASK_MAX_REG]; |
| 101 | int i; |
| 102 | |
| 103 | memset(ep_mask, 0, sizeof(ep_mask)); |
| 104 | |
| 105 | p2sb_soc_get_sb_mask(ep_mask, ARRAY_SIZE(ep_mask)); |
| 106 | |
| 107 | /* Remove the host accessing right to PSF register range. */ |
| 108 | for (i = 0; i < P2SB_EP_MASK_MAX_REG; i++) |
| 109 | p2sb_configure_endpoints(i, ep_mask[i]); |
| 110 | |
| 111 | p2sb_lock_endpoints(); |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 112 | } |
| 113 | |
| 114 | static void read_resources(struct device *dev) |
| 115 | { |
| 116 | /* |
| 117 | * There's only one resource on the P2SB device. It's also already |
| 118 | * manually set to a fixed address in earlier boot stages. |
Patrick Rudolph | 8d7a89b | 2019-10-04 09:22:27 +0200 | [diff] [blame] | 119 | * The following code makes sure that it doesn't change if the device |
| 120 | * is visible and the resource allocator is being run. |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 121 | */ |
| 122 | mmio_resource(dev, PCI_BASE_ADDRESS_0, P2SB_BAR / KiB, P2SB_SIZE / KiB); |
| 123 | } |
| 124 | |
| 125 | static const struct device_operations device_ops = { |
| 126 | .read_resources = read_resources, |
| 127 | .set_resources = DEVICE_NOOP, |
Subrata Banik | 6bbc91a | 2017-12-07 14:55:51 +0530 | [diff] [blame] | 128 | .ops_pci = &pci_dev_ops_pci, |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 129 | }; |
| 130 | |
| 131 | static const unsigned short pci_device_ids[] = { |
| 132 | PCI_DEVICE_ID_INTEL_APL_P2SB, |
| 133 | PCI_DEVICE_ID_INTEL_GLK_P2SB, |
Maxim Polyakov | 571d07d | 2019-08-22 13:11:32 +0300 | [diff] [blame] | 134 | PCI_DEVICE_ID_INTEL_LWB_P2SB, |
| 135 | PCI_DEVICE_ID_INTEL_LWB_P2SB_SUPER, |
Patrick Rudolph | 8d7a89b | 2019-10-04 09:22:27 +0200 | [diff] [blame] | 136 | PCI_DEVICE_ID_INTEL_SKL_LP_P2SB, |
| 137 | PCI_DEVICE_ID_INTEL_SKL_P2SB, |
| 138 | PCI_DEVICE_ID_INTEL_KBL_P2SB, |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 139 | PCI_DEVICE_ID_INTEL_CNL_P2SB, |
praveen hodagatta pranesh | e26c4a4 | 2018-09-20 03:49:45 +0800 | [diff] [blame] | 140 | PCI_DEVICE_ID_INTEL_CNP_H_P2SB, |
Aamir Bohra | 9eac039 | 2018-06-30 12:07:04 +0530 | [diff] [blame] | 141 | PCI_DEVICE_ID_INTEL_ICL_P2SB, |
Ronak Kanabar | da7ffb48 | 2019-02-05 01:51:13 +0530 | [diff] [blame] | 142 | PCI_DEVICE_ID_INTEL_CMP_P2SB, |
Gaggery Tsai | 12a651c | 2019-12-05 11:23:20 -0800 | [diff] [blame] | 143 | PCI_DEVICE_ID_INTEL_CMP_H_P2SB, |
Ravi Sarawadi | 6b5bf40 | 2019-10-21 22:25:04 -0700 | [diff] [blame] | 144 | PCI_DEVICE_ID_INTEL_TGL_P2SB, |
Tan, Lean Sheng | 2613609 | 2020-01-20 19:13:56 -0800 | [diff] [blame] | 145 | PCI_DEVICE_ID_INTEL_EHL_P2SB, |
Meera Ravindranath | 3f4af0d | 2020-02-12 16:01:22 +0530 | [diff] [blame] | 146 | PCI_DEVICE_ID_INTEL_JSP_P2SB, |
Lijian Zhao | a3cbbf7 | 2017-10-26 11:59:14 -0700 | [diff] [blame] | 147 | 0, |
| 148 | }; |
| 149 | |
| 150 | static const struct pci_driver pmc __pci_driver = { |
| 151 | .ops = &device_ops, |
| 152 | .vendor = PCI_VENDOR_ID_INTEL, |
| 153 | .devices = pci_device_ids, |
| 154 | }; |