Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 2 | |
Felix Held | c79c64b | 2023-06-01 21:52:05 +0200 | [diff] [blame] | 3 | #include <soc/amd/common/acpi/pci_root.asl> |
Felix Held | 41a5954 | 2023-12-19 22:33:46 +0100 | [diff] [blame^] | 4 | #include "globalnvs.asl" |
Felix Held | c79c64b | 2023-06-01 21:52:05 +0200 | [diff] [blame] | 5 | |
Felix Held | 41a5954 | 2023-12-19 22:33:46 +0100 | [diff] [blame^] | 6 | /* Power state notification to ALIB */ |
| 7 | #include "pnot.asl" |
Felix Held | c79c64b | 2023-06-01 21:52:05 +0200 | [diff] [blame] | 8 | |
Felix Held | 41a5954 | 2023-12-19 22:33:46 +0100 | [diff] [blame^] | 9 | /* Contains the supported sleep states for this chipset */ |
| 10 | #include <soc/amd/common/acpi/sleepstates.asl> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 11 | |
Felix Held | 41a5954 | 2023-12-19 22:33:46 +0100 | [diff] [blame^] | 12 | /* Contains _SWS methods */ |
| 13 | #include <soc/amd/common/acpi/acpi_wake_source.asl> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 14 | |
Felix Held | 41a5954 | 2023-12-19 22:33:46 +0100 | [diff] [blame^] | 15 | /* System Bus */ |
| 16 | Scope(\_SB) { /* Start \_SB scope */ |
| 17 | /* global utility methods expected within the \_SB scope */ |
| 18 | #include <arch/x86/acpi/globutil.asl> |
Felix Held | 753827e | 2022-11-03 23:05:03 +0100 | [diff] [blame] | 19 | |
Felix Held | 41a5954 | 2023-12-19 22:33:46 +0100 | [diff] [blame^] | 20 | ROOT_BRIDGE(PCI0) |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 21 | |
Felix Held | 41a5954 | 2023-12-19 22:33:46 +0100 | [diff] [blame^] | 22 | Scope(PCI0) { |
| 23 | /* Describe the AMD Northbridge */ |
| 24 | #include "northbridge.asl" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 25 | |
Felix Held | 41a5954 | 2023-12-19 22:33:46 +0100 | [diff] [blame^] | 26 | /* Describe the AMD Fusion Controller Hub */ |
| 27 | #include <soc/amd/common/acpi/lpc.asl> |
| 28 | #include <soc/amd/common/acpi/platform.asl> |
| 29 | } |
Tim Van Patten | 9244358 | 2022-08-23 16:06:33 -0600 | [diff] [blame] | 30 | |
Felix Held | 41a5954 | 2023-12-19 22:33:46 +0100 | [diff] [blame^] | 31 | /* PCI IRQ mapping for the Southbridge */ |
| 32 | #include "pci_int_defs.asl" |
| 33 | |
| 34 | /* Describe PCI INT[A-H] for the Southbridge */ |
| 35 | #include <soc/amd/common/acpi/pci_int.asl> |
| 36 | |
| 37 | /* Describe the MMIO devices in the FCH */ |
| 38 | #include "mmio.asl" |
| 39 | |
| 40 | /* Add GPIO library */ |
| 41 | #include <soc/amd/common/acpi/gpio_bank_lib.asl> |
| 42 | |
| 43 | #if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC) |
| 44 | #include <soc/amd/common/acpi/dptc.asl> |
| 45 | #endif |
| 46 | |
| 47 | } /* End \_SB scope */ |