Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 2 | |
Felix Held | c79c64b | 2023-06-01 21:52:05 +0200 | [diff] [blame] | 3 | #include <soc/amd/common/acpi/pci_root.asl> |
| 4 | |
| 5 | ROOT_BRIDGE(PCI0) |
| 6 | |
| 7 | Scope(PCI0) { |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 8 | /* Describe the AMD Northbridge */ |
| 9 | #include "northbridge.asl" |
| 10 | |
| 11 | /* Describe the AMD Fusion Controller Hub */ |
Felix Held | 7838109 | 2023-06-01 21:56:39 +0200 | [diff] [blame] | 12 | #include <soc/amd/common/acpi/lpc.asl> |
| 13 | #include <soc/amd/common/acpi/platform.asl> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 14 | } |
| 15 | |
Felix Held | 753827e | 2022-11-03 23:05:03 +0100 | [diff] [blame] | 16 | /* PCI IRQ mapping for the Southbridge */ |
| 17 | #include "pci_int_defs.asl" |
| 18 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 19 | /* Describe PCI INT[A-H] for the Southbridge */ |
Raul E Rangel | afe1fe5 | 2021-05-04 16:48:25 -0600 | [diff] [blame] | 20 | #include <soc/amd/common/acpi/pci_int.asl> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 21 | |
Felix Held | 4d6c39d | 2023-06-01 23:03:13 +0200 | [diff] [blame] | 22 | /* Describe the MMIO devices in the FCH */ |
| 23 | #include "mmio.asl" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 24 | |
| 25 | /* Add GPIO library */ |
| 26 | #include <soc/amd/common/acpi/gpio_bank_lib.asl> |
Tim Van Patten | 9244358 | 2022-08-23 16:06:33 -0600 | [diff] [blame] | 27 | |
Tim Van Patten | 9b3112c | 2022-09-13 10:08:49 -0600 | [diff] [blame] | 28 | #if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC) |
Tim Van Patten | 9244358 | 2022-08-23 16:06:33 -0600 | [diff] [blame] | 29 | #include <soc/amd/common/acpi/dptc.asl> |
Tim Van Patten | 9b3112c | 2022-09-13 10:08:49 -0600 | [diff] [blame] | 30 | #endif |