| Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 2 | |
| 3 | Device(PCI0) { |
| 4 | /* Describe the AMD Northbridge */ |
| 5 | #include "northbridge.asl" |
| 6 | |
| 7 | /* Describe the AMD Fusion Controller Hub */ |
| 8 | #include "sb_pci0_fch.asl" |
| 9 | } |
| 10 | |
| 11 | /* Describe PCI INT[A-H] for the Southbridge */ |
| Raul E Rangel | afe1fe5 | 2021-05-04 16:48:25 -0600 | [diff] [blame] | 12 | #include <soc/amd/common/acpi/pci_int.asl> |
| Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 13 | |
| Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 14 | /* Describe the devices in the Southbridge */ |
| 15 | #include "sb_fch.asl" |
| 16 | |
| 17 | /* Add GPIO library */ |
| 18 | #include <soc/amd/common/acpi/gpio_bank_lib.asl> |
| Tim Van Patten | 9244358 | 2022-08-23 16:06:33 -0600 | [diff] [blame^] | 19 | |
| 20 | #include <soc/amd/common/acpi/dptc.asl> |