| Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
| Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 3 | |
| 4 | Device(PCI0) { |
| 5 | /* Describe the AMD Northbridge */ |
| 6 | #include "northbridge.asl" |
| 7 | |
| 8 | /* Describe the AMD Fusion Controller Hub */ |
| 9 | #include "sb_pci0_fch.asl" |
| 10 | } |
| 11 | |
| 12 | /* Describe PCI INT[A-H] for the Southbridge */ |
| 13 | #include "pci_int.asl" |
| 14 | |
| 15 | /* Describe the devices in the Southbridge */ |
| 16 | #include "sb_fch.asl" |
| 17 | |
| 18 | /* Add GPIO library */ |
| 19 | #include <soc/amd/common/acpi/gpio_bank_lib.asl> |