Stefan Reinauer | 425b61e | 2015-03-15 04:29:35 +0100 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2009-2010 coresystems GmbH |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; version 2 of the License. |
| 9 | ## |
| 10 | ## This program is distributed in the hope that it will be useful, |
| 11 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ## GNU General Public License for more details. |
| 14 | ## |
| 15 | |
Stefan Reinauer | a48ca84 | 2015-04-04 01:58:28 +0200 | [diff] [blame] | 16 | config ARCH_X86 |
| 17 | bool |
| 18 | default n |
| 19 | select PCI |
| 20 | |
Stefan Reinauer | 6867120 | 2015-03-15 04:34:03 +0100 | [diff] [blame] | 21 | # stage selectors for x86 |
| 22 | |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 23 | config ARCH_BOOTBLOCK_X86_32 |
Gabe Black | 5fbfc91 | 2013-07-07 13:52:37 -0700 | [diff] [blame] | 24 | bool |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 25 | default n |
| 26 | select ARCH_X86 |
Andrey Petrov | 3bc543a | 2016-02-08 17:46:31 -0800 | [diff] [blame] | 27 | select BOOTBLOCK_CUSTOM if !C_ENVIRONMENT_BOOTBLOCK |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 28 | |
Stefan Reinauer | 77b1655 | 2015-01-14 19:51:47 +0100 | [diff] [blame] | 29 | config ARCH_VERSTAGE_X86_32 |
| 30 | bool |
| 31 | default n |
| 32 | |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 33 | config ARCH_ROMSTAGE_X86_32 |
| 34 | bool |
| 35 | default n |
| 36 | |
| 37 | config ARCH_RAMSTAGE_X86_32 |
| 38 | bool |
| 39 | default n |
Gabe Black | 5fbfc91 | 2013-07-07 13:52:37 -0700 | [diff] [blame] | 40 | |
Stefan Reinauer | 6867120 | 2015-03-15 04:34:03 +0100 | [diff] [blame] | 41 | # stage selectors for x64 |
| 42 | |
| 43 | config ARCH_BOOTBLOCK_X86_64 |
| 44 | bool |
| 45 | default n |
| 46 | select ARCH_X86 |
Andrey Petrov | 3bc543a | 2016-02-08 17:46:31 -0800 | [diff] [blame] | 47 | select BOOTBLOCK_CUSTOM if !C_ENVIRONMENT_BOOTBLOCK |
Stefan Reinauer | 6867120 | 2015-03-15 04:34:03 +0100 | [diff] [blame] | 48 | |
| 49 | config ARCH_VERSTAGE_X86_64 |
| 50 | bool |
| 51 | default n |
| 52 | |
| 53 | config ARCH_ROMSTAGE_X86_64 |
| 54 | bool |
| 55 | default n |
| 56 | |
| 57 | config ARCH_RAMSTAGE_X86_64 |
| 58 | bool |
| 59 | default n |
| 60 | |
Martin Roth | 0cd9ff8 | 2016-02-01 17:33:37 -0700 | [diff] [blame] | 61 | config USE_MARCH_586 |
| 62 | def_bool n |
| 63 | help |
| 64 | Allow a platform or processor to select to be compiled using |
| 65 | the '-march=i586' option instead of the typical '-march=i686' |
| 66 | |
Uwe Hermann | 168b11b | 2009-10-07 16:15:40 +0000 | [diff] [blame] | 67 | # This is an SMP option. It relates to starting up APs. |
| 68 | # It is usually set in mainboard/*/Kconfig. |
| 69 | # TODO: Improve description. |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 70 | config AP_IN_SIPI_WAIT |
| 71 | bool |
| 72 | default n |
Stefan Reinauer | 2a6f390 | 2012-10-15 13:38:09 -0700 | [diff] [blame] | 73 | depends on ARCH_X86 && SMP |
Ronald G. Minnich | 6ed39d9 | 2009-08-29 02:59:35 +0000 | [diff] [blame] | 74 | |
Kyösti Mälkki | f8c7c23 | 2012-04-06 04:03:50 +0300 | [diff] [blame] | 75 | # Aligns 16bit entry code in bootblock so that hyper-threading CPUs |
| 76 | # can boot AP CPUs to enable their shared caches. |
| 77 | config SIPI_VECTOR_IN_ROM |
| 78 | bool |
| 79 | default n |
| 80 | depends on ARCH_X86 |
| 81 | |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 82 | config RAMBASE |
| 83 | hex |
| 84 | default 0x100000 |
| 85 | |
Kyösti Mälkki | bec853e | 2016-06-15 02:25:00 +0300 | [diff] [blame] | 86 | config RAMTOP |
| 87 | hex |
| 88 | default 0x200000 |
| 89 | depends on ARCH_X86 |
| 90 | |
Alexandru Gagniuc | 6a62231 | 2015-10-27 10:27:30 -0700 | [diff] [blame] | 91 | # Traditionally BIOS region on SPI flash boot media was memory mapped right below |
| 92 | # 4G and it was the last region in the IFD. This way translation between CPU |
| 93 | # address space to flash address was trivial. However some IFDs on newer SoCs |
| 94 | # have BIOS region sandwiched between descriptor and other regions. Turning off |
| 95 | # this option enables soc code to provide custom mmap_boot.c which can be used to |
| 96 | # implement complex translation. |
| 97 | config X86_TOP4G_BOOTMEDIA_MAP |
| 98 | bool |
| 99 | default y |
| 100 | |
Ronald G. Minnich | b5e777c | 2013-07-22 20:17:18 +0200 | [diff] [blame] | 101 | # This is something you almost certainly don't want to mess with. |
| 102 | # How many SIPIs do we send when starting up APs and cores? |
| 103 | # The answer in 2000 or so was '2'. Nowadays, on many systems, |
| 104 | # it is 1. Set a safe default here, and you can override it |
| 105 | # on reasonable platforms. |
| 106 | config NUM_IPI_STARTS |
| 107 | int |
| 108 | default 2 |
| 109 | |
Patrick Georgi | 2063197a | 2010-02-09 12:21:10 +0000 | [diff] [blame] | 110 | config ROMCC |
| 111 | bool |
| 112 | default n |
| 113 | |
Kyösti Mälkki | 91fac61 | 2014-12-31 20:55:19 +0200 | [diff] [blame] | 114 | config LATE_CBMEM_INIT |
| 115 | def_bool n |
Kyösti Mälkki | 91fac61 | 2014-12-31 20:55:19 +0200 | [diff] [blame] | 116 | help |
| 117 | Enable this in chipset's Kconfig if northbridge does not implement |
| 118 | early get_top_of_ram() call for romstage. CBMEM tables will be |
| 119 | allocated late in ramstage, after PCI devices resources are known. |
| 120 | |
Naresh G Solanki | 04bb480 | 2016-12-13 21:16:46 +0530 | [diff] [blame] | 121 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 122 | hex |
| 123 | default 0xc00 |
| 124 | help |
| 125 | Increase this value if preram cbmem console is getting truncated |
| 126 | |
Stefan Reinauer | 8aedcbc | 2010-12-16 23:37:17 +0000 | [diff] [blame] | 127 | config PC80_SYSTEM |
| 128 | bool |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 129 | default y if ARCH_X86 |
Stefan Reinauer | 8aedcbc | 2010-12-16 23:37:17 +0000 | [diff] [blame] | 130 | |
Lee Leahy | fdc8c8b | 2016-06-07 08:45:17 -0700 | [diff] [blame] | 131 | config BOOTBLOCK_DEBUG_SPINLOOP |
| 132 | bool |
| 133 | default n |
| 134 | help |
| 135 | Add a spin (JMP .) in bootblock_crt0.S during early bootblock to wait |
| 136 | for a JTAG debugger to break into the execution sequence. |
| 137 | |
Kyösti Mälkki | 48e21ec | 2012-11-14 08:08:50 +0200 | [diff] [blame] | 138 | config BOOTBLOCK_MAINBOARD_INIT |
| 139 | string |
| 140 | |
Patrick Georgi | 1bb6828 | 2009-12-31 12:56:53 +0000 | [diff] [blame] | 141 | config BOOTBLOCK_NORTHBRIDGE_INIT |
| 142 | string |
| 143 | |
Lee Leahy | 5f31f49 | 2015-02-09 21:09:49 -0800 | [diff] [blame] | 144 | config BOOTBLOCK_RESETS |
| 145 | string |
| 146 | |
Lee Leahy | 2030d25 | 2016-06-05 18:41:00 -0700 | [diff] [blame] | 147 | config BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP |
| 148 | bool |
| 149 | default n |
| 150 | help |
| 151 | Select this value to provide a routine to save the BIST and timestamp |
| 152 | values. The default code places the BIST value in MM0 and the |
| 153 | timestamp value in MM2:MM1. Another file is necessary when the CPU |
| 154 | does not support the MMx register set. |
| 155 | |
Patrick Georgi | a865b17 | 2011-01-14 07:40:24 +0000 | [diff] [blame] | 156 | config HAVE_CMOS_DEFAULT |
| 157 | def_bool n |
Martin Roth | f76303e | 2016-11-16 15:45:22 -0700 | [diff] [blame] | 158 | depends on HAVE_OPTION_TABLE |
Patrick Georgi | a865b17 | 2011-01-14 07:40:24 +0000 | [diff] [blame] | 159 | |
| 160 | config CMOS_DEFAULT_FILE |
| 161 | string |
Denis 'GNUtoo' Carikli | 29a4355 | 2013-05-28 13:46:12 +0200 | [diff] [blame] | 162 | default "src/mainboard/$(MAINBOARDDIR)/cmos.default" |
Patrick Georgi | a865b17 | 2011-01-14 07:40:24 +0000 | [diff] [blame] | 163 | depends on HAVE_CMOS_DEFAULT |
| 164 | |
Patrick Georgi | 1bb6828 | 2009-12-31 12:56:53 +0000 | [diff] [blame] | 165 | config BOOTBLOCK_SOUTHBRIDGE_INIT |
| 166 | string |
Stefan Reinauer | 1b34226 | 2011-01-05 02:27:53 +0000 | [diff] [blame] | 167 | |
Patrick Georgi | d4d5e4d | 2012-03-16 19:28:15 +0100 | [diff] [blame] | 168 | config IOAPIC_INTERRUPTS_ON_FSB |
| 169 | bool |
| 170 | default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS |
| 171 | |
| 172 | config IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS |
| 173 | bool |
| 174 | default n |
| 175 | |
Patrick Georgi | 9aeb694 | 2012-10-05 21:54:38 +0200 | [diff] [blame] | 176 | config HPET_ADDRESS |
| 177 | hex |
| 178 | default 0xfed00000 if !HPET_ADDRESS_OVERRIDE |
| 179 | |
Stefan Reinauer | 8483344 | 2012-11-13 15:04:12 -0800 | [diff] [blame] | 180 | config ID_SECTION_OFFSET |
| 181 | hex |
| 182 | default 0x80 |
Patrick Georgi | c32a52c | 2015-06-22 21:10:34 +0200 | [diff] [blame] | 183 | |
Aaron Durbin | 65ac3d8 | 2016-02-11 14:36:19 -0600 | [diff] [blame] | 184 | # 64KiB default bootblock size when employing C_ENVIRONMENT_BOOTBLOCK. |
| 185 | config C_ENV_BOOTBLOCK_SIZE |
| 186 | hex |
| 187 | default 0x10000 |
Andrey Petrov | ccd300b | 2016-02-28 22:04:51 -0800 | [diff] [blame] | 188 | |
| 189 | # Default address romstage is to be linked at |
| 190 | config ROMSTAGE_ADDR |
| 191 | hex |
| 192 | default 0x2000000 |
| 193 | |
| 194 | # Default address verstage is to be linked at |
| 195 | config VERSTAGE_ADDR |
| 196 | hex |
| 197 | default 0x2000000 |
Aaron Durbin | 7f8afe0 | 2016-03-18 12:21:23 -0500 | [diff] [blame] | 198 | |
| 199 | # Use the post CAR infrastructure for tearing down cache-as-ram |
Elyes HAOUAS | 777ea89 | 2016-07-29 07:40:41 +0200 | [diff] [blame] | 200 | # from a program loaded in RAM and subsequently loading ramstage. |
Aaron Durbin | 7f8afe0 | 2016-03-18 12:21:23 -0500 | [diff] [blame] | 201 | config POSTCAR_STAGE |
| 202 | def_bool n |
Lee Leahy | d131ea3 | 2016-06-08 13:40:08 -0700 | [diff] [blame] | 203 | |
| 204 | config VERSTAGE_DEBUG_SPINLOOP |
| 205 | bool |
| 206 | default n |
| 207 | help |
| 208 | Add a spin (JMP .) in assembly_entry.S during early verstage to wait |
| 209 | for a JTAG debugger to break into the execution sequence. |
| 210 | |
| 211 | config ROMSTAGE_DEBUG_SPINLOOP |
| 212 | bool |
| 213 | default n |
| 214 | help |
| 215 | Add a spin (JMP .) in assembly_entry.S during early romstage to wait |
| 216 | for a JTAG debugger to break into the execution sequence. |