Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 1 | config ARCH_BOOTBLOCK_X86_32 |
Gabe Black | 5fbfc91 | 2013-07-07 13:52:37 -0700 | [diff] [blame] | 2 | bool |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 3 | default n |
| 4 | select ARCH_X86 |
| 5 | |
Stefan Reinauer | 77b1655 | 2015-01-14 19:51:47 +0100 | [diff] [blame] | 6 | config ARCH_VERSTAGE_X86_32 |
| 7 | bool |
| 8 | default n |
| 9 | |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 10 | config ARCH_ROMSTAGE_X86_32 |
| 11 | bool |
| 12 | default n |
| 13 | |
| 14 | config ARCH_RAMSTAGE_X86_32 |
| 15 | bool |
| 16 | default n |
Gabe Black | 5fbfc91 | 2013-07-07 13:52:37 -0700 | [diff] [blame] | 17 | |
Uwe Hermann | 168b11b | 2009-10-07 16:15:40 +0000 | [diff] [blame] | 18 | # This is an SMP option. It relates to starting up APs. |
| 19 | # It is usually set in mainboard/*/Kconfig. |
| 20 | # TODO: Improve description. |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 21 | config AP_IN_SIPI_WAIT |
| 22 | bool |
| 23 | default n |
Stefan Reinauer | 2a6f390 | 2012-10-15 13:38:09 -0700 | [diff] [blame] | 24 | depends on ARCH_X86 && SMP |
Ronald G. Minnich | 6ed39d9 | 2009-08-29 02:59:35 +0000 | [diff] [blame] | 25 | |
Kyösti Mälkki | f8c7c23 | 2012-04-06 04:03:50 +0300 | [diff] [blame] | 26 | # Aligns 16bit entry code in bootblock so that hyper-threading CPUs |
| 27 | # can boot AP CPUs to enable their shared caches. |
| 28 | config SIPI_VECTOR_IN_ROM |
| 29 | bool |
| 30 | default n |
| 31 | depends on ARCH_X86 |
| 32 | |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 33 | config RAMBASE |
| 34 | hex |
| 35 | default 0x100000 |
| 36 | |
| 37 | config STACK_SIZE |
| 38 | hex |
Stefan Reinauer | 9c03957 | 2012-10-15 13:39:00 -0700 | [diff] [blame] | 39 | default 0x1000 |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 40 | |
Ronald G. Minnich | b5e777c | 2013-07-22 20:17:18 +0200 | [diff] [blame] | 41 | # This is something you almost certainly don't want to mess with. |
| 42 | # How many SIPIs do we send when starting up APs and cores? |
| 43 | # The answer in 2000 or so was '2'. Nowadays, on many systems, |
| 44 | # it is 1. Set a safe default here, and you can override it |
| 45 | # on reasonable platforms. |
| 46 | config NUM_IPI_STARTS |
| 47 | int |
| 48 | default 2 |
| 49 | |
Patrick Georgi | 2063197a | 2010-02-09 12:21:10 +0000 | [diff] [blame] | 50 | config ROMCC |
| 51 | bool |
| 52 | default n |
| 53 | |
Kyösti Mälkki | 91fac61 | 2014-12-31 20:55:19 +0200 | [diff] [blame^] | 54 | config BROKEN_CAR_MIGRATE |
| 55 | def_bool n |
| 56 | help |
| 57 | Many boards use CAR_GLOBAL but have no EARLY_CBMEM_INIT and |
| 58 | manage CAR migration on S3 resume path only. Couple boards use |
| 59 | CAR_GLOBAL and never do CAR migration. |
| 60 | |
| 61 | config LATE_CBMEM_INIT |
| 62 | def_bool n |
| 63 | select BROKEN_CAR_MIGRATE |
| 64 | help |
| 65 | Enable this in chipset's Kconfig if northbridge does not implement |
| 66 | early get_top_of_ram() call for romstage. CBMEM tables will be |
| 67 | allocated late in ramstage, after PCI devices resources are known. |
| 68 | |
Stefan Reinauer | 8aedcbc | 2010-12-16 23:37:17 +0000 | [diff] [blame] | 69 | config PC80_SYSTEM |
| 70 | bool |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 71 | default y if ARCH_X86 |
Stefan Reinauer | 8aedcbc | 2010-12-16 23:37:17 +0000 | [diff] [blame] | 72 | |
Kyösti Mälkki | 48e21ec | 2012-11-14 08:08:50 +0200 | [diff] [blame] | 73 | config BOOTBLOCK_MAINBOARD_INIT |
| 74 | string |
| 75 | |
Patrick Georgi | 1bb6828 | 2009-12-31 12:56:53 +0000 | [diff] [blame] | 76 | config BOOTBLOCK_NORTHBRIDGE_INIT |
| 77 | string |
| 78 | |
Patrick Georgi | a865b17 | 2011-01-14 07:40:24 +0000 | [diff] [blame] | 79 | config HAVE_CMOS_DEFAULT |
| 80 | def_bool n |
| 81 | |
| 82 | config CMOS_DEFAULT_FILE |
| 83 | string |
Denis 'GNUtoo' Carikli | 29a4355 | 2013-05-28 13:46:12 +0200 | [diff] [blame] | 84 | default "src/mainboard/$(MAINBOARDDIR)/cmos.default" |
Patrick Georgi | a865b17 | 2011-01-14 07:40:24 +0000 | [diff] [blame] | 85 | depends on HAVE_CMOS_DEFAULT |
| 86 | |
Patrick Georgi | 1bb6828 | 2009-12-31 12:56:53 +0000 | [diff] [blame] | 87 | config BOOTBLOCK_SOUTHBRIDGE_INIT |
| 88 | string |
Stefan Reinauer | 1b34226 | 2011-01-05 02:27:53 +0000 | [diff] [blame] | 89 | |
Patrick Georgi | d4d5e4d | 2012-03-16 19:28:15 +0100 | [diff] [blame] | 90 | config IOAPIC_INTERRUPTS_ON_FSB |
| 91 | bool |
| 92 | default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS |
| 93 | |
| 94 | config IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS |
| 95 | bool |
| 96 | default n |
| 97 | |
Patrick Georgi | 9aeb694 | 2012-10-05 21:54:38 +0200 | [diff] [blame] | 98 | config HPET_ADDRESS |
| 99 | hex |
| 100 | default 0xfed00000 if !HPET_ADDRESS_OVERRIDE |
| 101 | |
Stefan Reinauer | 8483344 | 2012-11-13 15:04:12 -0800 | [diff] [blame] | 102 | config ID_SECTION_OFFSET |
| 103 | hex |
| 104 | default 0x80 |