Blame - src/arch/x86/Kconfig - coreboot

blob: 29f0514bca65415f23a5b04170c3da4c242644b1 [file] [log] [blame]

Stefan Reinauer	425b61e	2015-03-15 04:29:35 +0100	[diff] [blame]	1	##
				2	## This file is part of the coreboot project.
				3	##
				4	## Copyright (C) 2009-2010 coresystems GmbH
				5	##
				6	## This program is free software; you can redistribute it and/or modify
				7	## it under the terms of the GNU General Public License as published by
				8	## the Free Software Foundation; version 2 of the License.
				9	##
				10	## This program is distributed in the hope that it will be useful,
				11	## but WITHOUT ANY WARRANTY; without even the implied warranty of
				12	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
				13	## GNU General Public License for more details.
				14	##
				15
Stefan Reinauer	a48ca84	2015-04-04 01:58:28 +0200	[diff] [blame]	16	config ARCH_X86
				17	bool
				18	default n
				19	select PCI
				20
Furquan Shaikh	99ac98f	2014-04-23 10:18:48 -0700	[diff] [blame]	21	config ARCH_BOOTBLOCK_X86_32
Gabe Black	5fbfc91	2013-07-07 13:52:37 -0700	[diff] [blame]	22	bool
Furquan Shaikh	99ac98f	2014-04-23 10:18:48 -0700	[diff] [blame]	23	default n
				24	select ARCH_X86
				25
Stefan Reinauer	77b1655	2015-01-14 19:51:47 +0100	[diff] [blame]	26	config ARCH_VERSTAGE_X86_32
				27	bool
				28	default n
				29
Furquan Shaikh	99ac98f	2014-04-23 10:18:48 -0700	[diff] [blame]	30	config ARCH_ROMSTAGE_X86_32
				31	bool
				32	default n
				33
				34	config ARCH_RAMSTAGE_X86_32
				35	bool
				36	default n
Gabe Black	5fbfc91	2013-07-07 13:52:37 -0700	[diff] [blame]	37
Uwe Hermann	168b11b	2009-10-07 16:15:40 +0000	[diff] [blame]	38	# This is an SMP option. It relates to starting up APs.
				39	# It is usually set in mainboard/*/Kconfig.
				40	# TODO: Improve description.
Sven Schnelle	51676b1	2012-07-29 19:18:03 +0200	[diff] [blame]	41	config AP_IN_SIPI_WAIT
				42	bool
				43	default n
Stefan Reinauer	2a6f390	2012-10-15 13:38:09 -0700	[diff] [blame]	44	depends on ARCH_X86 && SMP
Ronald G. Minnich	6ed39d9	2009-08-29 02:59:35 +0000	[diff] [blame]	45
Kyösti Mälkki	f8c7c23	2012-04-06 04:03:50 +0300	[diff] [blame]	46	# Aligns 16bit entry code in bootblock so that hyper-threading CPUs
				47	# can boot AP CPUs to enable their shared caches.
				48	config SIPI_VECTOR_IN_ROM
				49	bool
				50	default n
				51	depends on ARCH_X86
				52
Patrick Georgi	0588d19	2009-08-12 15:00:51 +0000	[diff] [blame]	53	config RAMBASE
				54	hex
				55	default 0x100000
				56
Ronald G. Minnich	b5e777c	2013-07-22 20:17:18 +0200	[diff] [blame]	57	# This is something you almost certainly don't want to mess with.
				58	# How many SIPIs do we send when starting up APs and cores?
				59	# The answer in 2000 or so was '2'. Nowadays, on many systems,
				60	# it is 1. Set a safe default here, and you can override it
				61	# on reasonable platforms.
				62	config NUM_IPI_STARTS
				63	int
				64	default 2
				65
Patrick Georgi	2063197a	2010-02-09 12:21:10 +0000	[diff] [blame]	66	config ROMCC
				67	bool
				68	default n
				69
Kyösti Mälkki	91fac61	2014-12-31 20:55:19 +0200	[diff] [blame]	70	config LATE_CBMEM_INIT
				71	def_bool n
Kyösti Mälkki	91fac61	2014-12-31 20:55:19 +0200	[diff] [blame]	72	help
				73	Enable this in chipset's Kconfig if northbridge does not implement
				74	early get_top_of_ram() call for romstage. CBMEM tables will be
				75	allocated late in ramstage, after PCI devices resources are known.
				76
Stefan Reinauer	8aedcbc	2010-12-16 23:37:17 +0000	[diff] [blame]	77	config PC80_SYSTEM
				78	bool
Furquan Shaikh	99ac98f	2014-04-23 10:18:48 -0700	[diff] [blame]	79	default y if ARCH_X86
Stefan Reinauer	8aedcbc	2010-12-16 23:37:17 +0000	[diff] [blame]	80
Kyösti Mälkki	48e21ec	2012-11-14 08:08:50 +0200	[diff] [blame]	81	config BOOTBLOCK_MAINBOARD_INIT
				82	string
				83
Patrick Georgi	1bb6828	2009-12-31 12:56:53 +0000	[diff] [blame]	84	config BOOTBLOCK_NORTHBRIDGE_INIT
				85	string
				86
Lee Leahy	5f31f49	2015-02-09 21:09:49 -0800	[diff] [blame^]	87	config BOOTBLOCK_RESETS
				88	string
				89
Patrick Georgi	a865b17	2011-01-14 07:40:24 +0000	[diff] [blame]	90	config HAVE_CMOS_DEFAULT
				91	def_bool n
				92
				93	config CMOS_DEFAULT_FILE
				94	string
Denis 'GNUtoo' Carikli	29a4355	2013-05-28 13:46:12 +0200	[diff] [blame]	95	default "src/mainboard/$(MAINBOARDDIR)/cmos.default"
Patrick Georgi	a865b17	2011-01-14 07:40:24 +0000	[diff] [blame]	96	depends on HAVE_CMOS_DEFAULT
				97
Patrick Georgi	1bb6828	2009-12-31 12:56:53 +0000	[diff] [blame]	98	config BOOTBLOCK_SOUTHBRIDGE_INIT
				99	string
Stefan Reinauer	1b34226	2011-01-05 02:27:53 +0000	[diff] [blame]	100
Patrick Georgi	d4d5e4d	2012-03-16 19:28:15 +0100	[diff] [blame]	101	config IOAPIC_INTERRUPTS_ON_FSB
				102	bool
				103	default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
				104
				105	config IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
				106	bool
				107	default n
				108
Patrick Georgi	9aeb694	2012-10-05 21:54:38 +0200	[diff] [blame]	109	config HPET_ADDRESS
				110	hex
				111	default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
				112
Stefan Reinauer	8483344	2012-11-13 15:04:12 -0800	[diff] [blame]	113	config ID_SECTION_OFFSET
				114	hex
				115	default 0x80