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review.coreboot.org / coreboot / 3f882fafa069ce3c7cb39bdc80c73ade3f0daa46 / . / util / inteltool / cpu.c
blob: e322e81028b65de06a17b4023d092f60723ef877 [file] [log] [blame]
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]1/*
2 * inteltool - dump all registers on an Intel CPU + chipset based system.
3 *
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]4 * Copyright (C) 2008-2010 by coresystems GmbH
5 *
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]14 */
15
16#include <fcntl.h>
17#include <unistd.h>
18#include <stdio.h>
19#include <stdlib.h>
20#include <string.h>
21#include <errno.h>
22
23#include "inteltool.h"
24
Mathias Krause9beb5df2011-06-27 14:35:00 +0200[diff] [blame]25#ifdef __x86_64__
26# define BREG "%%rbx"
27#else
28# define BREG "%%ebx"
29#endif
30
Pratik Prajapati91664d42017-07-24 13:53:26 -0700[diff] [blame]31#define IA32_FEATURE_CONTROL 0x3a
32#define SGX_GLOBAL_ENABLED (1 << 18)
33#define FEATURE_CONTROL_LOCKED (1)
34#define MTRR_CAP_MSR 0xfe
35#define PRMRR_SUPPORTED (1 << 12)
36#define SGX_SUPPORTED (1 << 2)
37
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]38int fd_msr;
39
40unsigned int cpuid(unsigned int op)
41{
Stefan Reinauerf7f2f252009-09-01 09:52:14 +0000[diff] [blame]42 uint32_t ret;
43
Mathias Krause5782fee2011-03-09 11:30:55 +0100[diff] [blame]44#if defined(__PIC__) || defined(__DARWIN__) && !defined(__LP64__)
Stefan Reinauer1c60c882010-05-30 12:35:39 +0000[diff] [blame]45 asm volatile (
Mathias Krause9beb5df2011-06-27 14:35:00 +0200[diff] [blame]46 "push " BREG "\n\t"
47 "cpuid\n\t"
48 "pop " BREG "\n\t"
Stefan Reinauer1c60c882010-05-30 12:35:39 +0000[diff] [blame]49 : "=a" (ret) : "a" (op) : "%ecx", "%edx"
50 );
Stefan Reinauerf1824562009-04-22 23:17:44 +0000[diff] [blame]51#else
Stefan Reinauerf7f2f252009-09-01 09:52:14 +0000[diff] [blame]52 asm ("cpuid" : "=a" (ret) : "a" (op) : "%ebx", "%ecx", "%edx");
Stefan Reinauerf1824562009-04-22 23:17:44 +0000[diff] [blame]53#endif
Stefan Reinauerf7f2f252009-09-01 09:52:14 +0000[diff] [blame]54
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]55 return ret;
56}
57
Pratik Prajapati91664d42017-07-24 13:53:26 -0700[diff] [blame]58inline cpuid_result_t cpuid_ext(int op, unsigned int ecx)
59{
60 cpuid_result_t result;
61
62#ifndef __DARWIN__
63 asm volatile (
64 "mov %%ebx, %%edi;"
65 "cpuid;"
66 "mov %%ebx, %%esi;"
67 "mov %%edi, %%ebx;"
68 : "=a" (result.eax),
69 "=S" (result.ebx),
70 "=c" (result.ecx),
71 "=d" (result.edx)
72 : "0" (op), "2" (ecx)
73 : "edi");
74#endif
75 return result;
76}
77
Stefan Reinauerf7f2f252009-09-01 09:52:14 +0000[diff] [blame]78#ifndef __DARWIN__
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]79int msr_readerror = 0;
80
Jacob Garber6faccd12019-07-01 11:21:55 -0600[diff] [blame]81static msr_t rdmsr(int addr)
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]82{
Stefan Reinauera7b296d2011-11-14 12:40:34 -0800[diff] [blame]83 uint32_t buf[2];
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]84 msr_t msr = { 0xffffffff, 0xffffffff };
85
86 if (lseek(fd_msr, (off_t) addr, SEEK_SET) == -1) {
87 perror("Could not lseek() to MSR");
88 close(fd_msr);
89 exit(1);
90 }
91
92 if (read(fd_msr, buf, 8) == 8) {
Stefan Reinauera7b296d2011-11-14 12:40:34 -0800[diff] [blame]93 msr.lo = buf[0];
94 msr.hi = buf[1];
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]95 return msr;
96 }
97
98 if (errno == 5) {
99 printf(" (*)"); // Not all bits of the MSR could be read
100 msr_readerror = 1;
101 } else {
102 // A severe error.
103 perror("Could not read() MSR");
104 close(fd_msr);
105 exit(1);
106 }
107
108 return msr;
109}
Pratik Prajapati91664d42017-07-24 13:53:26 -0700[diff] [blame]110
111static int open_and_seek(int cpu, unsigned long msr, int mode, int *fd)
112{
Jacob Garber198c2e62019-07-01 11:04:41 -0600[diff] [blame]113 char dev[32];
Pratik Prajapati91664d42017-07-24 13:53:26 -0700[diff] [blame]114 char temp_string[50];
115
116 snprintf(dev, sizeof(dev), "/dev/cpu/%d/msr", cpu);
117 *fd = open(dev, mode);
118
119 if (*fd < 0) {
Maciej Suminskid5fb99e2017-08-09 11:46:41 +0200[diff] [blame]120 snprintf(temp_string, sizeof(temp_string), "open(\"%s\")", dev);
Pratik Prajapati91664d42017-07-24 13:53:26 -0700[diff] [blame]121 perror(temp_string);
122 return -1;
123 }
124
125 if (lseek(*fd, msr, SEEK_SET) == (off_t)-1) {
Maciej Suminskid5fb99e2017-08-09 11:46:41 +0200[diff] [blame]126 snprintf(temp_string, sizeof(temp_string), "lseek(%lu)", msr);
Pratik Prajapati91664d42017-07-24 13:53:26 -0700[diff] [blame]127 perror(temp_string);
128 close(*fd);
129 return -1;
130 }
131
132 return 0;
133}
134
Jacob Garber6faccd12019-07-01 11:21:55 -0600[diff] [blame]135static msr_t rdmsr_from_cpu(int cpu, unsigned long addr)
Pratik Prajapati91664d42017-07-24 13:53:26 -0700[diff] [blame]136{
137 int fd;
138 msr_t msr = { 0xffffffff, 0xffffffff };
139 uint32_t buf[2];
140 char temp_string[50];
141
142 if (open_and_seek(cpu, addr, O_RDONLY, &fd) < 0) {
Maciej Suminskid5fb99e2017-08-09 11:46:41 +0200[diff] [blame]143 snprintf(temp_string, sizeof(temp_string),
144 "Could not read MSR for CPU#%d", cpu);
Pratik Prajapati91664d42017-07-24 13:53:26 -0700[diff] [blame]145 perror(temp_string);
146 }
147
148 if (read(fd, buf, 8) == 8) {
149 msr.lo = buf[0];
150 msr.hi = buf[1];
151 }
152
153 close(fd);
154
155 return msr;
156}
157
Jacob Garber6faccd12019-07-01 11:21:55 -0600[diff] [blame]158static int get_number_of_cpus(void)
Pratik Prajapati91664d42017-07-24 13:53:26 -0700[diff] [blame]159{
160 return sysconf(_SC_NPROCESSORS_ONLN);
161}
162
Maxim Polyakov9af10bf2019-10-08 17:33:59 +0300[diff] [blame]163static int get_number_of_cores(void)
164{
165 return sysconf(_SC_NPROCESSORS_CONF);
166}
167
Jacob Garber6faccd12019-07-01 11:21:55 -0600[diff] [blame]168static int is_sgx_supported(int cpunum)
Pratik Prajapati91664d42017-07-24 13:53:26 -0700[diff] [blame]169{
170 cpuid_result_t cpuid_regs;
171 msr_t msr;
172
173 /* CPUID leaf 0x7 subleaf 0x0 to detect SGX support
174 details are mentioned in Intel SDM Chap.36- section 36.7 */
175 cpuid_regs = cpuid_ext(0x7, 0x0);
176 msr = rdmsr_from_cpu(cpunum, MTRR_CAP_MSR);
177 return ((cpuid_regs.ebx & SGX_SUPPORTED) && (msr.lo & PRMRR_SUPPORTED));
178}
179
Jacob Garber6faccd12019-07-01 11:21:55 -0600[diff] [blame]180static int is_sgx_enabled(int cpunum)
Pratik Prajapati91664d42017-07-24 13:53:26 -0700[diff] [blame]181{
182 msr_t data;
183 data = rdmsr_from_cpu(cpunum, IA32_FEATURE_CONTROL);
184 return (data.lo & SGX_GLOBAL_ENABLED);
185}
186
Jacob Garber6faccd12019-07-01 11:21:55 -0600[diff] [blame]187static int is_sgx_locked(int cpunum)
Pratik Prajapati91664d42017-07-24 13:53:26 -0700[diff] [blame]188{
189 msr_t data;
190 data = rdmsr_from_cpu(cpunum, IA32_FEATURE_CONTROL);
191 return (data.lo & FEATURE_CONTROL_LOCKED);
192}
193
Stefan Reinauer1162f252008-12-04 15:18:20 +0000[diff] [blame]194#endif
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]195
Pratik Prajapati91664d42017-07-24 13:53:26 -0700[diff] [blame]196int print_sgx(void)
197{
198 int error = -1;
199#ifndef __DARWIN__
200 int ncpus = get_number_of_cpus();
201 int i = 0;
Pratik Prajapati91664d42017-07-24 13:53:26 -0700[diff] [blame]202
203 printf("\n============= Dumping INTEL SGX status =============");
204
205 if (ncpus < 1) {
Maciej Suminskid5fb99e2017-08-09 11:46:41 +0200[diff] [blame]206 perror("Failed to get number of CPUs");
Pratik Prajapati91664d42017-07-24 13:53:26 -0700[diff] [blame]207 error = -1;
208 } else {
209 printf("\nNumber of CPUs = %d\n", ncpus);
210 for (i = 0; i < ncpus ; i++) {
211
212 printf("------------- CPU %d ----------------\n", i);
213 printf("SGX supported : %s\n",
214 is_sgx_supported(i) ? "YES" : "NO");
215 printf("SGX enabled : %s\n",
216 is_sgx_enabled(i) ? "YES" : "NO");
217 printf("Feature Control locked : %s\n",
218 is_sgx_locked(i) ? "YES" : "NO");
219 }
220 error = 0;
221 }
222 printf("====================================================\n");
223#endif
224 return error;
225}
226
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]227int print_intel_core_msrs(void)
228{
Maxim Polyakov9af10bf2019-10-08 17:33:59 +0300[diff] [blame]229 unsigned int i, core, id, core_num = get_number_of_cores();
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]230 msr_t msr;
231
232#define IA32_PLATFORM_ID 0x0017
233#define EBL_CR_POWERON 0x002a
234#define FSB_CLK_STS 0x00cd
235#define IA32_TIME_STAMP_COUNTER 0x0010
236#define IA32_APIC_BASE 0x001b
237
238 typedef struct {
239 int number;
240 char *name;
241 } msr_entry_t;
242
Tobias Diedrich3645e612010-11-27 14:44:19 +0000[diff] [blame]243 /* Pentium III */
244 static const msr_entry_t model67x_global_msrs[] = {
245 { 0x0000, "IA32_P5_MC_ADDR" },
246 { 0x0001, "IA32_P5_MC_TYPE" },
247 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
248 { 0x0017, "IA32_PLATFORM_ID" },
249 { 0x001b, "IA32_APIC_BASE" },
250 { 0x002a, "EBL_CR_POWERON" },
251 { 0x0033, "TEST_CTL" },
252 //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO
253 { 0x0088, "BBL_CR_D0" },
254 { 0x0089, "BBL_CR_D1" },
255 { 0x008a, "BBL_CR_D2" },
256 { 0x008b, "IA32_BIOS_SIGN_ID" },
257 { 0x00c1, "PERFCTR0" },
258 { 0x00c2, "PERFCTR1" },
259 { 0x00fe, "IA32_MTRRCAP" },
260 { 0x0116, "BBL_CR_ADDR" },
261 { 0x0118, "BBL_CR_DECC" },
262 { 0x0119, "BBL_CR_CTL" },
263 //{ 0x011a, "BBL_CR_TRIG" },
264 { 0x011b, "BBL_CR_BUSY" },
265 { 0x011e, "BBL_CR_CTL3" },
266 { 0x0174, "IA32_SYSENTER_CS" },
267 { 0x0175, "IA32_SYSENTER_ESP" },
268 { 0x0176, "IA32_SYSENTER_EIP" },
269 { 0x0179, "IA32_MCG_CAP" },
270 { 0x017a, "IA32_MCG_STATUS" },
271 { 0x017b, "IA32_MCG_CTL" },
272 { 0x0186, "IA32_PERF_EVNTSEL0" },
273 { 0x0187, "IA32_PERF_EVNTSEL1" },
274 { 0x01d9, "IA32_DEBUGCTL" },
275 { 0x01db, "MSR_LASTBRANCHFROMIP" },
276 { 0x01dc, "MSR_LASTBRANCHTOIP" },
277 { 0x01dd, "MSR_LASTINTFROMIP" },
278 { 0x01de, "MSR_LASTINTTOIP" },
279 { 0x01e0, "MSR_ROB_CR_BKUPTMPDR6" },
280 { 0x0200, "IA32_MTRR_PHYSBASE0" },
281 { 0x0201, "IA32_MTRR_PHYSMASK0" },
282 { 0x0202, "IA32_MTRR_PHYSBASE1" },
283 { 0x0203, "IA32_MTRR_PHYSMASK1" },
284 { 0x0204, "IA32_MTRR_PHYSBASE2" },
285 { 0x0205, "IA32_MTRR_PHYSMASK2" },
286 { 0x0206, "IA32_MTRR_PHYSBASE3" },
287 { 0x0207, "IA32_MTRR_PHYSMASK3" },
288 { 0x0208, "IA32_MTRR_PHYSBASE4" },
289 { 0x0209, "IA32_MTRR_PHYSMASK4" },
290 { 0x020a, "IA32_MTRR_PHYSBASE5" },
291 { 0x020b, "IA32_MTRR_PHYSMASK5" },
292 { 0x020c, "IA32_MTRR_PHYSBASE6" },
293 { 0x020d, "IA32_MTRR_PHYSMASK6" },
294 { 0x020e, "IA32_MTRR_PHYSBASE7" },
295 { 0x020f, "IA32_MTRR_PHYSMASK7" },
296 { 0x0250, "IA32_MTRR_FIX64K_00000" },
297 { 0x0258, "IA32_MTRR_FIX16K_80000" },
298 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
299 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
300 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
301 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
302 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
303 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
304 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
305 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
306 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
307 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
308 { 0x0400, "IA32_MC0_CTL" },
309 { 0x0401, "IA32_MC0_STATUS" },
310 { 0x0402, "IA32_MC0_ADDR" },
311 //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO
312 { 0x0404, "IA32_MC1_CTL" },
313 { 0x0405, "IA32_MC1_STATUS" },
314 { 0x0406, "IA32_MC1_ADDR" },
315 //{ 0x0407, "IA32_MC1_MISC" }, // Seems to be RO
316 { 0x0408, "IA32_MC2_CTL" },
317 { 0x0409, "IA32_MC2_STATUS" },
318 { 0x040a, "IA32_MC2_ADDR" },
319 //{ 0x040b, "IA32_MC2_MISC" }, // Seems to be RO
320 { 0x040c, "IA32_MC4_CTL" },
321 { 0x040d, "IA32_MC4_STATUS" },
322 { 0x040e, "IA32_MC4_ADDR" },
323 //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO
324 { 0x0410, "IA32_MC3_CTL" },
325 { 0x0411, "IA32_MC3_STATUS" },
326 { 0x0412, "IA32_MC3_ADDR" },
327 //{ 0x0413, "IA32_MC3_MISC" }, // Seems to be RO
328 };
329
Stefan Reinauer04844812010-02-22 11:26:06 +0000[diff] [blame]330 static const msr_entry_t model6bx_global_msrs[] = {
331 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
332 { 0x0017, "IA32_PLATFORM_ID" },
333 { 0x001b, "IA32_APIC_BASE" },
334 { 0x002a, "EBL_CR_POWERON" },
335 { 0x0033, "TEST_CTL" },
336 { 0x003f, "THERM_DIODE_OFFSET" },
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]337 //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO
Stefan Reinauer04844812010-02-22 11:26:06 +0000[diff] [blame]338 { 0x008b, "IA32_BIOS_SIGN_ID" },
339 { 0x00c1, "PERFCTR0" },
340 { 0x00c2, "PERFCTR1" },
341 { 0x011e, "BBL_CR_CTL3" },
342 { 0x0179, "IA32_MCG_CAP" },
343 { 0x017a, "IA32_MCG_STATUS" },
344 { 0x0198, "IA32_PERF_STATUS" },
345 { 0x0199, "IA32_PERF_CONTROL" },
346 { 0x019a, "IA32_CLOCK_MODULATION" },
347 { 0x01a0, "IA32_MISC_ENABLES" },
348 { 0x01d9, "IA32_DEBUGCTL" },
349 { 0x0200, "IA32_MTRR_PHYSBASE0" },
350 { 0x0201, "IA32_MTRR_PHYSMASK0" },
351 { 0x0202, "IA32_MTRR_PHYSBASE1" },
352 { 0x0203, "IA32_MTRR_PHYSMASK1" },
353 { 0x0204, "IA32_MTRR_PHYSBASE2" },
354 { 0x0205, "IA32_MTRR_PHYSMASK2" },
355 { 0x0206, "IA32_MTRR_PHYSBASE3" },
356 { 0x0207, "IA32_MTRR_PHYSMASK3" },
357 { 0x0208, "IA32_MTRR_PHYSBASE4" },
358 { 0x0209, "IA32_MTRR_PHYSMASK4" },
359 { 0x020a, "IA32_MTRR_PHYSBASE5" },
360 { 0x020b, "IA32_MTRR_PHYSMASK5" },
361 { 0x020c, "IA32_MTRR_PHYSBASE6" },
362 { 0x020d, "IA32_MTRR_PHYSMASK6" },
363 { 0x020e, "IA32_MTRR_PHYSBASE7" },
364 { 0x020f, "IA32_MTRR_PHYSMASK7" },
365 { 0x0250, "IA32_MTRR_FIX64K_00000" },
366 { 0x0258, "IA32_MTRR_FIX16K_80000" },
367 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
368 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
369 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
370 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
371 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
372 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
373 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
374 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
375 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
376 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
377 { 0x0400, "IA32_MC0_CTL" },
378 { 0x0401, "IA32_MC0_STATUS" },
379 { 0x0402, "IA32_MC0_ADDR" },
380 //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO
381 { 0x040c, "IA32_MC4_CTL" },
382 { 0x040d, "IA32_MC4_STATUS" },
383 { 0x040e, "IA32_MC4_ADDR" },
384 //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO
385 };
386
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]387 static const msr_entry_t model6ex_global_msrs[] = {
388 { 0x0017, "IA32_PLATFORM_ID" },
389 { 0x002a, "EBL_CR_POWERON" },
390 { 0x00cd, "FSB_CLOCK_STS" },
391 { 0x00ce, "FSB_CLOCK_VCC" },
392 { 0x00e2, "CLOCK_CST_CONFIG_CONTROL" },
393 { 0x00e3, "PMG_IO_BASE_ADDR" },
394 { 0x00e4, "PMG_IO_CAPTURE_ADDR" },
395 { 0x00ee, "EXT_CONFIG" },
396 { 0x011e, "BBL_CR_CTL3" },
397 { 0x0194, "CLOCK_FLEX_MAX" },
398 { 0x0198, "IA32_PERF_STATUS" },
399 { 0x01a0, "IA32_MISC_ENABLES" },
400 { 0x01aa, "PIC_SENS_CFG" },
401 { 0x0400, "IA32_MC0_CTL" },
402 { 0x0401, "IA32_MC0_STATUS" },
403 { 0x0402, "IA32_MC0_ADDR" },
404 //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO
405 { 0x040c, "IA32_MC4_CTL" },
406 { 0x040d, "IA32_MC4_STATUS" },
407 { 0x040e, "IA32_MC4_ADDR" },
408 //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO
409 };
410
411 static const msr_entry_t model6ex_per_core_msrs[] = {
412 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
413 { 0x001b, "IA32_APIC_BASE" },
414 { 0x003a, "IA32_FEATURE_CONTROL" },
415 { 0x003f, "IA32_TEMPERATURE_OFFSET" },
416 //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO
417 { 0x008b, "IA32_BIOS_SIGN_ID" },
418 { 0x00e7, "IA32_MPERF" },
419 { 0x00e8, "IA32_APERF" },
420 { 0x00fe, "IA32_MTRRCAP" },
421 { 0x015f, "DTS_CAL_CTRL" },
422 { 0x0179, "IA32_MCG_CAP" },
423 { 0x017a, "IA32_MCG_STATUS" },
424 { 0x0199, "IA32_PERF_CONTROL" },
425 { 0x019a, "IA32_CLOCK_MODULATION" },
426 { 0x019b, "IA32_THERM_INTERRUPT" },
427 { 0x019c, "IA32_THERM_STATUS" },
428 { 0x019d, "GV_THERM" },
429 { 0x01d9, "IA32_DEBUGCTL" },
430 { 0x0200, "IA32_MTRR_PHYSBASE0" },
431 { 0x0201, "IA32_MTRR_PHYSMASK0" },
432 { 0x0202, "IA32_MTRR_PHYSBASE1" },
433 { 0x0203, "IA32_MTRR_PHYSMASK1" },
434 { 0x0204, "IA32_MTRR_PHYSBASE2" },
435 { 0x0205, "IA32_MTRR_PHYSMASK2" },
436 { 0x0206, "IA32_MTRR_PHYSBASE3" },
437 { 0x0207, "IA32_MTRR_PHYSMASK3" },
438 { 0x0208, "IA32_MTRR_PHYSBASE4" },
439 { 0x0209, "IA32_MTRR_PHYSMASK4" },
440 { 0x020a, "IA32_MTRR_PHYSBASE5" },
441 { 0x020b, "IA32_MTRR_PHYSMASK5" },
442 { 0x020c, "IA32_MTRR_PHYSBASE6" },
443 { 0x020d, "IA32_MTRR_PHYSMASK6" },
444 { 0x020e, "IA32_MTRR_PHYSBASE7" },
445 { 0x020f, "IA32_MTRR_PHYSMASK7" },
446 { 0x0250, "IA32_MTRR_FIX64K_00000" },
447 { 0x0258, "IA32_MTRR_FIX16K_80000" },
448 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
449 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
450 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
451 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
452 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
453 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
454 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
455 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
456 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
457 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
458 //{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO
459 };
460
461 static const msr_entry_t model6fx_global_msrs[] = {
462 { 0x0017, "IA32_PLATFORM_ID" },
463 { 0x002a, "EBL_CR_POWERON" },
464 { 0x003f, "IA32_TEMPERATURE_OFFSET" },
465 { 0x00a8, "EMTTM_CR_TABLE0" },
466 { 0x00a9, "EMTTM_CR_TABLE1" },
467 { 0x00aa, "EMTTM_CR_TABLE2" },
468 { 0x00ab, "EMTTM_CR_TABLE3" },
469 { 0x00ac, "EMTTM_CR_TABLE4" },
470 { 0x00ad, "EMTTM_CR_TABLE5" },
471 { 0x00cd, "FSB_CLOCK_STS" },
472 { 0x00e2, "PMG_CST_CONFIG_CONTROL" },
473 { 0x00e3, "PMG_IO_BASE_ADDR" },
474 { 0x00e4, "PMG_IO_CAPTURE_ADDR" },
475 { 0x00ee, "EXT_CONFIG" },
476 { 0x011e, "BBL_CR_CTL3" },
477 { 0x0194, "CLOCK_FLEX_MAX" },
478 { 0x0198, "IA32_PERF_STATUS" },
479 { 0x01a0, "IA32_MISC_ENABLES" },
480 { 0x01aa, "PIC_SENS_CFG" },
481 { 0x0400, "IA32_MC0_CTL" },
482 { 0x0401, "IA32_MC0_STATUS" },
483 { 0x0402, "IA32_MC0_ADDR" },
484 //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO
485 { 0x040c, "IA32_MC4_CTL" },
486 { 0x040d, "IA32_MC4_STATUS" },
487 { 0x040e, "IA32_MC4_ADDR" },
488 //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO
489 };
490
491 static const msr_entry_t model6fx_per_core_msrs[] = {
492 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
493 { 0x001b, "IA32_APIC_BASE" },
494 { 0x003a, "IA32_FEATURE_CONTROL" },
495 //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO
496 { 0x008b, "IA32_BIOS_SIGN_ID" },
497 { 0x00e1, "SMM_CST_MISC_INFO" },
498 { 0x00e7, "IA32_MPERF" },
499 { 0x00e8, "IA32_APERF" },
500 { 0x00fe, "IA32_MTRRCAP" },
501 { 0x0179, "IA32_MCG_CAP" },
502 { 0x017a, "IA32_MCG_STATUS" },
503 { 0x0199, "IA32_PERF_CONTROL" },
504 { 0x019a, "IA32_THERM_CTL" },
505 { 0x019b, "IA32_THERM_INTERRUPT" },
506 { 0x019c, "IA32_THERM_STATUS" },
507 { 0x019d, "MSR_THERM2_CTL" },
508 { 0x01d9, "IA32_DEBUGCTL" },
509 { 0x0200, "IA32_MTRR_PHYSBASE0" },
510 { 0x0201, "IA32_MTRR_PHYSMASK0" },
511 { 0x0202, "IA32_MTRR_PHYSBASE1" },
512 { 0x0203, "IA32_MTRR_PHYSMASK1" },
513 { 0x0204, "IA32_MTRR_PHYSBASE2" },
514 { 0x0205, "IA32_MTRR_PHYSMASK2" },
515 { 0x0206, "IA32_MTRR_PHYSBASE3" },
516 { 0x0207, "IA32_MTRR_PHYSMASK3" },
517 { 0x0208, "IA32_MTRR_PHYSBASE4" },
518 { 0x0209, "IA32_MTRR_PHYSMASK4" },
519 { 0x020a, "IA32_MTRR_PHYSBASE5" },
520 { 0x020b, "IA32_MTRR_PHYSMASK5" },
521 { 0x020c, "IA32_MTRR_PHYSBASE6" },
522 { 0x020d, "IA32_MTRR_PHYSMASK6" },
523 { 0x020e, "IA32_MTRR_PHYSBASE7" },
524 { 0x020f, "IA32_MTRR_PHYSMASK7" },
525 { 0x0250, "IA32_MTRR_FIX64K_00000" },
526 { 0x0258, "IA32_MTRR_FIX16K_80000" },
527 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
528 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
529 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
530 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
531 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
532 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
533 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
534 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
535 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
536 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
537 //{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO
538 };
539
Pat Erleyca3548e2010-04-21 06:23:19 +0000[diff] [blame]540 /* Pentium 4 and XEON */
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]541 /*
542 * All MSRs per
Pat Erleyca3548e2010-04-21 06:23:19 +0000[diff] [blame]543 *
Idwer Vollering312fc962010-12-17 22:34:58 +0000[diff] [blame]544 * Intel 64 and IA-32 Architectures Software Developer's Manual
545 * Volume 3B: System Programming Guide, Part 2
Pat Erleyca3548e2010-04-21 06:23:19 +0000[diff] [blame]546 *
Idwer Vollering312fc962010-12-17 22:34:58 +0000[diff] [blame]547 * Table B-5, B-7
Pat Erleyca3548e2010-04-21 06:23:19 +0000[diff] [blame]548 */
Idwer Vollering312fc962010-12-17 22:34:58 +0000[diff] [blame]549 static const msr_entry_t modelf2x_global_msrs[] = {
550 { 0x0000, "IA32_P5_MC_ADDR" },
551 { 0x0001, "IA32_P5_MC_TYPE" },
552 /* 0x6: Not available in model 2. */
553 { 0x0017, "IA32_PLATFORM_ID" },
554 { 0x002a, "MSR_EBC_HARD_POWERON" },
Elyes HAOUASe3e2bb02016-07-26 18:34:14 +0200[diff] [blame]555 { 0x002b, "MSR_EBC_SOFT_POWERON" },
Idwer Vollering312fc962010-12-17 22:34:58 +0000[diff] [blame]556 /* 0x2c: Not available in model 2. */
557// WRITE ONLY { 0x0079, "IA32_BIOS_UPDT_TRIG" },
558 { 0x019c, "IA32_THERM_STATUS" },
559 /* 0x19d: Not available in model 2. */
560 { 0x01a0, "IA32_MISC_ENABLE" },
561 /* 0x1a1: Not available in model 2. */
562 { 0x0200, "IA32_MTRR_PHYSBASE0" },
563 { 0x0201, "IA32_MTRR_PHYSMASK0" },
564 { 0x0202, "IA32_MTRR_PHYSBASE1" },
565 { 0x0203, "IA32_MTRR_PHYSMASK1" },
566 { 0x0204, "IA32_MTRR_PHYSBASE2" },
567 { 0x0205, "IA32_MTRR_PHYSMASK2" },
568 { 0x0206, "IA32_MTRR_PHYSBASE3" },
569 { 0x0207, "IA32_MTRR_PHYSMASK3" },
570 { 0x0208, "IA32_MTRR_PHYSBASE4" },
571 { 0x0209, "IA32_MTRR_PHYSMASK4" },
572 { 0x020a, "IA32_MTRR_PHYSBASE5" },
573 { 0x020b, "IA32_MTRR_PHYSMASK5" },
574 { 0x020c, "IA32_MTRR_PHYSBASE6" },
575 { 0x020d, "IA32_MTRR_PHYSMASK6" },
576 { 0x020e, "IA32_MTRR_PHYSBASE7" },
577 { 0x020f, "IA32_MTRR_PHYSMASK7" },
578 { 0x0250, "IA32_MTRR_FIX64K_00000" },
579 { 0x0258, "IA32_MTRR_FIX16K_80000" },
580 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
581 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
582 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
583 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
584 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
585 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
586 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
587 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
588 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
589 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
590 { 0x0300, "MSR_BPU_COUNTER0" },
591 { 0x0301, "MSR_BPU_COUNTER1" },
592 { 0x0302, "MSR_BPU_COUNTER2" },
593 { 0x0303, "MSR_BPU_COUNTER3" },
594 { 0x0304, "MSR_MS_COUNTER0" },
595 { 0x0305, "MSR_MS_COUNTER1" },
596 { 0x0306, "MSR_MS_COUNTER2" },
597 { 0x0307, "MSR_MS_COUNTER3" },
598 { 0x0308, "MSR_FLAME_COUNTER0" },
599 { 0x0309, "MSR_FLAME_COUNTER1" },
600 { 0x030a, "MSR_FLAME_COUNTER2" },
601 { 0x030b, "MSR_FLAME_COUNTER3" },
602 { 0x030c, "MSR_IQ_COUNTER0" },
603 { 0x030d, "MSR_IQ_COUNTER1" },
604 { 0x030e, "MSR_IQ_COUNTER2" },
605 { 0x030f, "MSR_IQ_COUNTER3" },
606 { 0x0310, "MSR_IQ_COUNTER4" },
607 { 0x0311, "MSR_IQ_COUNTER5" },
608 { 0x0360, "MSR_BPU_CCCR0" },
609 { 0x0361, "MSR_BPU_CCCR1" },
610 { 0x0362, "MSR_BPU_CCCR2" },
611 { 0x0363, "MSR_BPU_CCCR3" },
612 { 0x0364, "MSR_MS_CCCR0" },
613 { 0x0365, "MSR_MS_CCCR1" },
614 { 0x0366, "MSR_MS_CCCR2" },
615 { 0x0367, "MSR_MS_CCCR3" },
616 { 0x0368, "MSR_FLAME_CCCR0" },
617 { 0x0369, "MSR_FLAME_CCCR1" },
618 { 0x036a, "MSR_FLAME_CCCR2" },
619 { 0x036b, "MSR_FLAME_CCCR3" },
620 { 0x036c, "MSR_IQ_CCCR0" },
621 { 0x036d, "MSR_IQ_CCCR1" },
622 { 0x036e, "MSR_IQ_CCCR2" },
623 { 0x036f, "MSR_IQ_CCCR3" },
624 { 0x0370, "MSR_IQ_CCCR4" },
625 { 0x0371, "MSR_IQ_CCCR5" },
626 { 0x03a0, "MSR_BSU_ESCR0" },
627 { 0x03a1, "MSR_BSU_ESCR1" },
628 { 0x03a2, "MSR_FSB_ESCR0" },
629 { 0x03a3, "MSR_FSB_ESCR1" },
630 { 0x03a4, "MSR_FIRM_ESCR0" },
631 { 0x03a5, "MSR_FIRM_ESCR1" },
632 { 0x03a6, "MSR_FLAME_ESCR0" },
633 { 0x03a7, "MSR_FLAME_ESCR1" },
634 { 0x03a8, "MSR_DAC_ESCR0" },
635 { 0x03a9, "MSR_DAC_ESCR1" },
636 { 0x03aa, "MSR_MOB_ESCR0" },
637 { 0x03ab, "MSR_MOB_ESCR1" },
638 { 0x03ac, "MSR_PMH_ESCR0" },
639 { 0x03ad, "MSR_PMH_ESCR1" },
640 { 0x03ae, "MSR_SAAT_ESCR0" },
641 { 0x03af, "MSR_SAAT_ESCR1" },
642 { 0x03b0, "MSR_U2L_ESCR0" },
643 { 0x03b1, "MSR_U2L_ESCR1" },
644 { 0x03b2, "MSR_BPU_ESCR0" },
645 { 0x03b3, "MSR_BPU_ESCR1" },
646 { 0x03b4, "MSR_IS_ESCR0" },
647 { 0x03b5, "MSR_BPU_ESCR1" },
648 { 0x03b6, "MSR_ITLB_ESCR0" },
649 { 0x03b7, "MSR_ITLB_ESCR1" },
650 { 0x03b8, "MSR_CRU_ESCR0" },
651 { 0x03b9, "MSR_CRU_ESCR1" },
652 { 0x03ba, "MSR_IQ_ESCR0" },
653 { 0x03bb, "MSR_IQ_ESCR1" },
654 { 0x03bc, "MSR_RAT_ESCR0" },
655 { 0x03bd, "MSR_RAT_ESCR1" },
656 { 0x03be, "MSR_SSU_ESCR0" },
657 { 0x03c0, "MSR_MS_ESCR0" },
658 { 0x03c1, "MSR_MS_ESCR1" },
659 { 0x03c2, "MSR_TBPU_ESCR0" },
660 { 0x03c3, "MSR_TBPU_ESCR1" },
661 { 0x03c4, "MSR_TC_ESCR0" },
662 { 0x03c5, "MSR_TC_ESCR1" },
663 { 0x03c8, "MSR_IX_ESCR0" },
664 { 0x03c9, "MSR_IX_ESCR1" },
665 { 0x03ca, "MSR_ALF_ESCR0" },
666 { 0x03cb, "MSR_ALF_ESCR1" },
667 { 0x03cc, "MSR_CRU_ESCR2" },
668 { 0x03cd, "MSR_CRU_ESCR3" },
669 { 0x03e0, "MSR_CRU_ESCR4" },
670 { 0x03e1, "MSR_CRU_ESCR5" },
671 { 0x03f0, "MSR_TC_PRECISE_EVENT" },
672 { 0x03f1, "MSR_PEBS_ENABLE" },
673 { 0x03f2, "MSR_PEBS_MATRIX_VERT" },
674
675 /*
676 * All MCX_ADDR and MCX_MISC MSRs depend on a bit being
677 * set in MCX_STATUS.
678 */
679 { 0x400, "IA32_MC0_CTL" },
680 { 0x401, "IA32_MC0_STATUS" },
681 { 0x402, "IA32_MC0_ADDR" },
682 { 0x403, "IA32_MC0_MISC" },
683 { 0x404, "IA32_MC1_CTL" },
684 { 0x405, "IA32_MC1_STATUS" },
685 { 0x406, "IA32_MC1_ADDR" },
686 { 0x407, "IA32_MC1_MISC" },
687 { 0x408, "IA32_MC2_CTL" },
688 { 0x409, "IA32_MC2_STATUS" },
689 { 0x40a, "IA32_MC2_ADDR" },
690 { 0x40b, "IA32_MC2_MISC" },
691 { 0x40c, "IA32_MC3_CTL" },
692 { 0x40d, "IA32_MC3_STATUS" },
693 { 0x40e, "IA32_MC3_ADDR" },
694 { 0x40f, "IA32_MC3_MISC" },
695 { 0x410, "IA32_MC4_CTL" },
696 { 0x411, "IA32_MC4_STATUS" },
697 { 0x412, "IA32_MC4_ADDR" },
698 { 0x413, "IA32_MC4_MISC" },
699 };
700
701 static const msr_entry_t modelf2x_per_core_msrs[] = {
702 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
703 { 0x001b, "IA32_APIC_BASE" },
704 /* 0x3a: Not available in model 2. */
705 { 0x008b, "IA32_BIOS_SIGN_ID" },
706 /* 0x9b: Not available in model 2. */
707 { 0x00fe, "IA32_MTRRCAP" },
708 { 0x0174, "IA32_SYSENTER_CS" },
709 { 0x0175, "IA32_SYSENTER_ESP" },
710 { 0x0176, "IA32_SYSENTER_EIP" },
711 { 0x0179, "IA32_MCG_CAP" },
712 { 0x017a, "IA32_MCG_STATUS" },
713 { 0x017b, "IA32_MCG_CTL" },
714 { 0x0180, "MSR_MCG_RAX" },
715 { 0x0181, "MSR_MCG_RBX" },
716 { 0x0182, "MSR_MCG_RCX" },
717 { 0x0183, "MSR_MCG_RDX" },
718 { 0x0184, "MSR_MCG_RSI" },
719 { 0x0185, "MSR_MCG_RDI" },
720 { 0x0186, "MSR_MCG_RBP" },
721 { 0x0187, "MSR_MCG_RSP" },
722 { 0x0188, "MSR_MCG_RFLAGS" },
723 { 0x0189, "MSR_MCG_RIP" },
724 { 0x018a, "MSR_MCG_MISC" },
725 /* 0x18b-0x18f: Reserved */
726 { 0x0190, "MSR_MCG_R8" },
727 { 0x0191, "MSR_MCG_R9" },
728 { 0x0192, "MSR_MCG_R10" },
729 { 0x0193, "MSR_MCG_R11" },
730 { 0x0194, "MSR_MCG_R12" },
731 { 0x0195, "MSR_MCG_R13" },
732 { 0x0196, "MSR_MCG_R14" },
733 { 0x0197, "MSR_MCG_R15" },
734 /* 0x198: Not available in model 2. */
735 /* 0x199: Not available in model 2. */
736 { 0x019a, "IA32_CLOCK_MODULATION" },
737 { 0x019b, "IA32_THERM_INTERRUPT" },
738 { 0x01a0, "IA32_MISC_ENABLE" },
739 { 0x01d7, "MSR_LER_FROM_LIP" },
740 { 0x01d8, "MSR_LER_TO_LIP" },
741 { 0x01d9, "MSR_DEBUGCTLA" },
742 { 0x01da, "MSR_LASTBRANCH_TOS" },
743 { 0x01db, "MSR_LASTBRANCH_0" },
744 { 0x01dd, "MSR_LASTBRANCH_2" },
745 { 0x01de, "MSR_LASTBRANCH_3" },
746 { 0x0277, "IA32_PAT" },
747 /* 0x480-0x48b : Not available in model 2. */
748 { 0x0600, "IA32_DS_AREA" },
749 /* 0x0680 - 0x06cf Branch Records Skipped */
750 };
751
Pat Erleyca3548e2010-04-21 06:23:19 +0000[diff] [blame]752 static const msr_entry_t modelf4x_global_msrs[] = {
753 { 0x0000, "IA32_P5_MC_ADDR" },
754 { 0x0001, "IA32_P5_MC_TYPE" },
755 { 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" },
756 { 0x0017, "IA32_PLATFORM_ID" },
757 { 0x002a, "MSR_EBC_HARD_POWERON" },
Elyes HAOUASe3e2bb02016-07-26 18:34:14 +0200[diff] [blame]758 { 0x002b, "MSR_EBC_SOFT_POWERON" },
Pat Erleyca3548e2010-04-21 06:23:19 +0000[diff] [blame]759 { 0x002c, "MSR_EBC_FREQUENCY_ID" },
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]760// WRITE ONLY { 0x0079, "IA32_BIOS_UPDT_TRIG" },
Pat Erleyca3548e2010-04-21 06:23:19 +0000[diff] [blame]761 { 0x019c, "IA32_THERM_STATUS" },
762 { 0x019d, "MSR_THERM2_CTL" },
763 { 0x01a0, "IA32_MISC_ENABLE" },
764 { 0x01a1, "MSR_PLATFORM_BRV" },
765 { 0x0200, "IA32_MTRR_PHYSBASE0" },
766 { 0x0201, "IA32_MTRR_PHYSMASK0" },
767 { 0x0202, "IA32_MTRR_PHYSBASE1" },
768 { 0x0203, "IA32_MTRR_PHYSMASK1" },
769 { 0x0204, "IA32_MTRR_PHYSBASE2" },
770 { 0x0205, "IA32_MTRR_PHYSMASK2" },
771 { 0x0206, "IA32_MTRR_PHYSBASE3" },
772 { 0x0207, "IA32_MTRR_PHYSMASK3" },
773 { 0x0208, "IA32_MTRR_PHYSBASE4" },
774 { 0x0209, "IA32_MTRR_PHYSMASK4" },
775 { 0x020a, "IA32_MTRR_PHYSBASE5" },
776 { 0x020b, "IA32_MTRR_PHYSMASK5" },
777 { 0x020c, "IA32_MTRR_PHYSBASE6" },
778 { 0x020d, "IA32_MTRR_PHYSMASK6" },
779 { 0x020e, "IA32_MTRR_PHYSBASE7" },
780 { 0x020f, "IA32_MTRR_PHYSMASK7" },
781 { 0x0250, "IA32_MTRR_FIX64K_00000" },
782 { 0x0258, "IA32_MTRR_FIX16K_80000" },
783 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
784 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
785 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
786 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
787 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
788 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
789 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
790 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
791 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
792 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
793 { 0x0300, "MSR_BPU_COUNTER0" },
794 { 0x0301, "MSR_BPU_COUNTER1" },
795 { 0x0302, "MSR_BPU_COUNTER2" },
796 { 0x0303, "MSR_BPU_COUNTER3" },
797 /* Skipped through 0x3ff for now*/
798
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]799 /* All MCX_ADDR AND MCX_MISC MSRs depend on a bit being
Pat Erleyca3548e2010-04-21 06:23:19 +0000[diff] [blame]800 * set in MCX_STATUS */
801 { 0x400, "IA32_MC0_CTL" },
802 { 0x401, "IA32_MC0_STATUS" },
803 { 0x402, "IA32_MC0_ADDR" },
804 { 0x403, "IA32_MC0_MISC" },
805 { 0x404, "IA32_MC1_CTL" },
806 { 0x405, "IA32_MC1_STATUS" },
807 { 0x406, "IA32_MC1_ADDR" },
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]808 { 0x407, "IA32_MC1_MISC" },
Pat Erleyca3548e2010-04-21 06:23:19 +0000[diff] [blame]809 { 0x408, "IA32_MC2_CTL" },
810 { 0x409, "IA32_MC2_STATUS" },
811 { 0x40a, "IA32_MC2_ADDR" },
812 { 0x40b, "IA32_MC2_MISC" },
813 { 0x40c, "IA32_MC3_CTL" },
814 { 0x40d, "IA32_MC3_STATUS" },
815 { 0x40e, "IA32_MC3_ADDR" },
816 { 0x40f, "IA32_MC3_MISC" },
817 { 0x410, "IA32_MC4_CTL" },
818 { 0x411, "IA32_MC4_STATUS" },
819 { 0x412, "IA32_MC4_ADDR" },
820 { 0x413, "IA32_MC4_MISC" },
821 };
822
823 static const msr_entry_t modelf4x_per_core_msrs[] = {
824 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
825 { 0x001b, "IA32_APIC_BASE" },
826 { 0x003a, "IA32_FEATURE_CONTROL" },
827 { 0x008b, "IA32_BIOS_SIGN_ID" },
828 { 0x009b, "IA32_SMM_MONITOR_CTL" },
829 { 0x00fe, "IA32_MTRRCAP" },
830 { 0x0174, "IA32_SYSENTER_CS" },
831 { 0x0175, "IA32_SYSENTER_ESP" },
832 { 0x0176, "IA32_SYSENTER_EIP" },
833 { 0x0179, "IA32_MCG_CAP" },
834 { 0x017a, "IA32_MCG_STATUS" },
835 { 0x0180, "MSR_MCG_RAX" },
836 { 0x0181, "MSR_MCG_RBX" },
837 { 0x0182, "MSR_MCG_RCX" },
838 { 0x0183, "MSR_MCG_RDX" },
839 { 0x0184, "MSR_MCG_RSI" },
840 { 0x0185, "MSR_MCG_RDI" },
841 { 0x0186, "MSR_MCG_RBP" },
842 { 0x0187, "MSR_MCG_RSP" },
843 { 0x0188, "MSR_MCG_RFLAGS" },
844 { 0x0189, "MSR_MCG_RIP" },
845 { 0x018a, "MSR_MCG_MISC" },
846 // 0x18b-f Reserved
847 { 0x0190, "MSR_MCG_R8" },
848 { 0x0191, "MSR_MCG_R9" },
849 { 0x0192, "MSR_MCG_R10" },
850 { 0x0193, "MSR_MCG_R11" },
851 { 0x0194, "MSR_MCG_R12" },
852 { 0x0195, "MSR_MCG_R13" },
853 { 0x0196, "MSR_MCG_R14" },
854 { 0x0197, "MSR_MCG_R15" },
855 { 0x0198, "IA32_PERF_STATUS" },
856 { 0x0199, "IA32_PERF_CTL" },
857 { 0x019a, "IA32_CLOCK_MODULATION" },
858 { 0x019b, "IA32_THERM_INTERRUPT" },
859 { 0x01a0, "IA32_MISC_ENABLE" }, // Bit 34 is Core Specific
860 { 0x01d7, "MSR_LER_FROM_LIP" },
861 { 0x01d8, "MSR_LER_TO_LIP" },
862 { 0x01d9, "MSR_DEBUGCTLA" },
863 { 0x01da, "MSR_LASTBRANCH_TOS" },
864 { 0x0277, "IA32_PAT" },
865 /** Virtualization
866 { 0x480, "IA32_VMX_BASIC" },
867 through
868 { 0x48b, "IA32_VMX_PROCBASED_CTLS2" },
869 Not implemented in my CPU
870 */
871 { 0x0600, "IA32_DS_AREA" },
872 /* 0x0680 - 0x06cf Branch Records Skipped */
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]873
Pat Erleyca3548e2010-04-21 06:23:19 +0000[diff] [blame]874 };
875
Elyes HAOUASdfe8d642018-01-31 21:29:00 +0100[diff] [blame]876 /*
877 * 64-ia-32-architectures-software-developer-vol-3c-part-3-manual
878 * September 2016
879 */
880 static const msr_entry_t modelf6x_global_msrs[] = {
881 { 0x0000, "IA32_P5_MC_ADDR" },
882 { 0x0001, "IA32_P5_MC_TYPE" },
883 { 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" },
884 { 0x0017, "IA32_PLATFORM_ID" },
885 { 0x002a, "MSR_EBC_HARD_POWERON" },
886 { 0x002b, "MSR_EBC_SOFT_POWERON" },
887 { 0x002c, "MSR_EBC_FREQUENCY_ID" },
888// WRITE ONLY { 0x0079, "IA32_BIOS_UPDT_TRIG" },
889 { 0x019c, "IA32_THERM_STATUS" },
890 { 0x019d, "MSR_THERM2_CTL" },
891 { 0x01a0, "IA32_MISC_ENABLE" },
892 { 0x01a1, "MSR_PLATFORM_BRV" },
893 { 0x0200, "IA32_MTRR_PHYSBASE0" },
894 { 0x0201, "IA32_MTRR_PHYSMASK0" },
895 { 0x0202, "IA32_MTRR_PHYSBASE1" },
896 { 0x0203, "IA32_MTRR_PHYSMASK1" },
897 { 0x0204, "IA32_MTRR_PHYSBASE2" },
898 { 0x0205, "IA32_MTRR_PHYSMASK2" },
899 { 0x0206, "IA32_MTRR_PHYSBASE3" },
900 { 0x0207, "IA32_MTRR_PHYSMASK3" },
901 { 0x0208, "IA32_MTRR_PHYSBASE4" },
902 { 0x0209, "IA32_MTRR_PHYSMASK4" },
903 { 0x020a, "IA32_MTRR_PHYSBASE5" },
904 { 0x020b, "IA32_MTRR_PHYSMASK5" },
905 { 0x020c, "IA32_MTRR_PHYSBASE6" },
906 { 0x020d, "IA32_MTRR_PHYSMASK6" },
907 { 0x020e, "IA32_MTRR_PHYSBASE7" },
908 { 0x020f, "IA32_MTRR_PHYSMASK7" },
909 { 0x0250, "IA32_MTRR_FIX64K_00000" },
910 { 0x0258, "IA32_MTRR_FIX16K_80000" },
911 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
912 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
913 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
914 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
915 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
916 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
917 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
918 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
919 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
920 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
921 { 0x0300, "MSR_BPU_COUNTER0" },
922 { 0x0301, "MSR_BPU_COUNTER1" },
923 { 0x0302, "MSR_BPU_COUNTER2" },
924 { 0x0303, "MSR_BPU_COUNTER3" },
925 { 0x0304, "MSR_MS_COUNTER0" },
926 { 0x0305, "MSR_MS_COUNTER1" },
927 { 0x0306, "MSR_MS_COUNTER2" },
928 { 0x0307, "MSR_MS_COUNTER3" },
929 { 0x0308, "MSR_FLAME_COUNTER0" },
930 { 0x0309, "MSR_FLAME_COUNTER1" },
931 { 0x030a, "MSR_FLAME_COUNTER2" },
932 { 0x030b, "MSR_FLAME_COUNTER3" },
933 { 0x030c, "MSR_IQ_COUNTER0" },
934 { 0x030d, "MSR_IQ_COUNTER1" },
935 { 0x030e, "MSR_IQ_COUNTER2" },
936 { 0x030f, "MSR_IQ_COUNTER3" },
937 { 0x0310, "MSR_IQ_COUNTER4" },
938 { 0x0311, "MSR_IQ_COUNTER5" },
939 { 0x0360, "MSR_BPU_CCCR0" },
940 { 0x0361, "MSR_BPU_CCCR1" },
941 { 0x0362, "MSR_BPU_CCCR2" },
942 { 0x0363, "MSR_BPU_CCCR3" },
943 { 0x0364, "MSR_MS_CCCR0" },
944 { 0x0365, "MSR_MS_CCCR1" },
945 { 0x0366, "MSR_MS_CCCR2" },
946 { 0x0367, "MSR_MS_CCCR3" },
947 { 0x0368, "MSR_FLAME_CCCR0" },
948 { 0x0369, "MSR_FLAME_CCCR1" },
949 { 0x036A, "MSR_FLAME_CCCR2" },
950 { 0x036B, "MSR_FLAME_CCCR3" },
951 { 0x036C, "MSR_IQ_CCCR0" },
952 { 0x036D, "MSR_IQ_CCCR1" },
953 { 0x036E, "MSR_IQ_CCCR2" },
954 { 0x036F, "MSR_IQ_CCCR3" },
955 { 0x0370, "MSR_IQ_CCCR4" },
956 { 0x0371, "MSR_IQ_CCCR5" },
957 { 0x03A0, "MSR_BSU_ESCR0" },
958 { 0x03A1, "MSR_BSU_ESCR1" },
959 { 0x03A2, "MSR_FSB_ESCR0" },
960 { 0x03A3, "MSR_FSB_ESCR1" },
961 { 0x03A4, "MSR_FIRM_ESCR0" },
962 { 0x03A5, "MSR_FIRM_ESCR1" },
963 { 0x03A6, "MSR_FLAME_ESCR0" },
964 { 0x03A7, "MSR_FLAME_ESCR1" },
965 { 0x03A8, "MSR_DAC_ESCR0" },
966 { 0x03A9, "MSR_DAC_ESCR1" },
967 { 0x03AA, "MSR_MOB_ESCR0" },
968 { 0x03AB, "MSR_MOB_ESCR1" },
969 { 0x03AC, "MSR_PMH_ESCR0" },
970 { 0x03AD, "MSR_PMH_ESCR1" },
971 { 0x03AE, "MSR_SAAT_ESCR0" },
972 { 0x03AF, "MSR_SAAT_ESCR1" },
973 { 0x03B0, "MSR_U2L_ESCR0" },
974 { 0x03B1, "MSR_U2L_ESCR1" },
975 { 0x03B2, "MSR_BPU_ESCR0" },
976 { 0x03B3, "MSR_BPU_ESCR1" },
977 { 0x03B4, "MSR_IS_ESCR0" },
978 { 0x03B5, "MSR_IS_ESCR1" },
979 { 0x03B6, "MSR_ITLB_ESCR0" },
980 { 0x03B7, "MSR_ITLB_ESCR1" },
981 { 0x03B8, "MSR_CRU_ESCR0" },
982 { 0x03B9, "MSR_CRU_ESCR1" },
983 { 0x03BA, "MSR_IQ_ESCR0" },
984 { 0x03BB, "MSR_IQ_ESCR1" },
985 { 0x03BC, "MSR_RAT_ESCR0" },
986 { 0x03BD, "MSR_RAT_ESCR1" },
987 { 0x03BE, "MSR_SSU_ESCR0" },
988 { 0x03C0, "MSR_MS_ESCR0" },
989 { 0x03C1, "MSR_MS_ESCR1" },
990 { 0x03C2, "MSR_TBPU_ESCR0" },
991 { 0x03C3, "MSR_TBPU_ESCR1" },
992 { 0x03C4, "MSR_TC_ESCR0" },
993 { 0x03C5, "MSR_TC_ESCR1" },
994 { 0x03C8, "MSR_IX_ESCR0" },
995 { 0x03C9, "MSR_IX_ESCR1" },
996 { 0x03CA, "MSR_ALF_ESCR0" },
997 { 0x03CB, "MSR_ALF_ESCR1" },
998 { 0x03CC, "MSR_CRU_ESCR2" },
999 { 0x03CD, "MSR_CRU_ESCR3" },
1000 { 0x03E0, "MSR_CRU_ESCR4" },
1001 { 0x03E1, "MSR_CRU_ESCR5" },
1002 { 0x03F0, "MSR_TC_PRECISE_EVENT" },
1003 { 0x03F1, "MSR_PEBS_ENABLE" },
1004 { 0x03F2, "MSR_PEBS_MATRIX_VERT" },
1005 { 0x0400, "IA32_MC0_CTL" },
1006 { 0x0401, "IA32_MC0_STATUS" },
1007 { 0x0402, "IA32_MC0_ADDR" },
1008 { 0x0403, "IA32_MC0_MISC" },
1009 { 0x0404, "IA32_MC1_CTL" },
1010 { 0x0405, "IA32_MC1_STATUS" },
1011 { 0x0406, "IA32_MC1_ADDR" },
1012 { 0x0408, "IA32_MC2_CTL" },
1013 { 0x0409, "IA32_MC2_STATUS" },
1014 { 0x040b, "IA32_MC2_MISC" },
1015 { 0x040c, "IA32_MC3_CTL" },
1016 { 0x040d, "IA32_MC3_STATUS" },
1017 { 0x040e, "IA32_MC3_ADDR" },
1018 { 0x040f, "IA32_MC3_MISC" },
1019 };
1020
1021 static const msr_entry_t modelf6x_per_core_msrs[] = {
1022 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
1023 { 0x001b, "IA32_APIC_BASE" },
1024 { 0x008b, "IA32_BIOS_SIGN_ID" },
1025 { 0x00fe, "IA32_MTRRCAP" },
1026 { 0x0174, "IA32_SYSENTER_CS" },
1027 { 0x0175, "IA32_SYSENTER_ESP" },
1028 { 0x0176, "IA32_SYSENTER_EIP" },
1029 { 0x0179, "IA32_MCG_CAP" },
1030 { 0x017a, "IA32_MCG_STATUS" },
1031 { 0x0180, "MSR_MCG_RAX" },
1032 { 0x0181, "MSR_MCG_RBX" },
1033 { 0x0182, "MSR_MCG_RCX" },
1034 { 0x0183, "MSR_MCG_RDX" },
1035 { 0x0184, "MSR_MCG_RSI" },
1036 { 0x0185, "MSR_MCG_RDI" },
1037 { 0x0186, "MSR_MCG_RBP" },
1038 { 0x0187, "MSR_MCG_RSP" },
1039 { 0x0188, "MSR_MCG_RFLAGS" },
1040 { 0x0189, "MSR_MCG_RIP" },
1041 { 0x018a, "MSR_MCG_MISC" },
1042 { 0x0190, "MSR_MCG_R8" },
1043 { 0x0191, "MSR_MCG_R9" },
1044 { 0x0192, "MSR_MCG_R10" },
1045 { 0x0193, "MSR_MCG_R11" },
1046 { 0x0194, "MSR_MCG_R12" },
1047 { 0x0195, "MSR_MCG_R13" },
1048 { 0x0196, "MSR_MCG_R14" },
1049 { 0x0197, "MSR_MCG_R15" },
1050 { 0x0198, "IA32_PERF_STATUS" },
1051 { 0x0199, "IA32_PERF_CTL" },
1052 { 0x019a, "IA32_CLOCK_MODULATION" },
1053 { 0x019b, "IA32_THERM_INTERRUPT" },
1054 { 0x01A2, "MSR_TEMPERATURE_TARGET" },
1055 { 0x01d7, "MSR_LER_FROM_LIP" },
1056 { 0x01d8, "MSR_LER_TO_LIP" },
1057 { 0x01d9, "MSR_DEBUGCTLA" },
1058 { 0x01da, "MSR_LASTBRANCH_TOS" },
1059 { 0x0277, "IA32_PAT" },
1060 { 0x0600, "IA32_DS_AREA" },
1061 { 0x0680, "MSR_LASTBRANCH_0_FROM_IP" },
1062 { 0x0681, "MSR_LASTBRANCH_1_FROM_IP" },
1063 { 0x0682, "MSR_LASTBRANCH_2_FROM_IP" },
1064 { 0x0683, "MSR_LASTBRANCH_3_FROM_IP" },
1065 { 0x0684, "MSR_LASTBRANCH_4_FROM_IP" },
1066 { 0x0685, "MSR_LASTBRANCH_5_FROM_IP" },
1067 { 0x0686, "MSR_LASTBRANCH_6_FROM_IP" },
1068 { 0x0687, "MSR_LASTBRANCH_7_FROM_IP" },
1069 { 0x0688, "MSR_LASTBRANCH_8_FROM_IP" },
1070 { 0x0689, "MSR_LASTBRANCH_9_FROM_IP" },
1071 { 0x068a, "MSR_LASTBRANCH_10_FROM_IP" },
1072 { 0x068b, "MSR_LASTBRANCH_11_FROM_IP" },
1073 { 0x068c, "MSR_LASTBRANCH_12_FROM_IP" },
1074 { 0x068d, "MSR_LASTBRANCH_13_FROM_IP" },
1075 { 0x068e, "MSR_LASTBRANCH_14_FROM_IP" },
1076 { 0x068f, "MSR_LASTBRANCH_15_FROM_IP" },
1077 { 0x06c0, "MSR_LASTBRANCH_0_TO_IP" },
1078 { 0x06c1, "MSR_LASTBRANCH_1_TO_IP" },
1079 { 0x06c2, "MSR_LASTBRANCH_2_TO_IP" },
1080 { 0x06c3, "MSR_LASTBRANCH_3_TO_IP" },
1081 { 0x06c4, "MSR_LASTBRANCH_4_TO_IP" },
1082 { 0x06c5, "MSR_LASTBRANCH_5_TO_IP" },
1083 { 0x06c6, "MSR_LASTBRANCH_6_TO_IP" },
1084 { 0x06c7, "MSR_LASTBRANCH_7_TO_IP" },
1085 { 0x06c8, "MSR_LASTBRANCH_8_TO_IP" },
1086 { 0x06c9, "MSR_LASTBRANCH_9_TO_IP" },
1087 { 0x06ca, "MSR_LASTBRANCH_10_TO_IP" },
1088 { 0x06cb, "MSR_LASTBRANCH_11_TO_IP" },
1089 { 0x06cc, "MSR_LASTBRANCH_12_TO_IP" },
1090 { 0x06cd, "MSR_LASTBRANCH_13_TO_IP" },
1091 { 0x06ce, "MSR_LASTBRANCH_14_TO_IP" },
1092 { 0x06cf, "MSR_LASTBRANCH_15_TO_IP" },
1093 /* Intel Xeon processor 7100 with L3 */
1094// { 0x107CC, "MSR_EMON_L3_CTR_CTL0" },
1095// { 0x107CD, "MSR_EMON_L3_CTR_CTL1" },
1096// { 0x107CE, "MSR_EMON_L3_CTR_CTL2" },
1097// { 0x107CF, "MSR_EMON_L3_CTR_CTL3" },
1098// { 0x107D0, "MSR_EMON_L3_CTR_CTL4" },
1099// { 0x107D1, "MSR_EMON_L3_CTR_CTL5" },
1100// { 0x107D2, "MSR_EMON_L3_CTR_CTL6" },
1101// { 0x107D3, "MSR_EMON_L3_CTR_CTL7" },
1102 };
1103
Olivier Langlois70f39872013-01-25 00:49:46 -0500[diff] [blame]1104 /* Atom N455
1105 *
1106 * This should apply to the following processors:
1107 * 06_1CH
1108 * 06_26H
1109 * 06_27H
1110 * 06_35
1111 * 06_36
1112 */
1113 /*
1114 * All MSRs per
1115 *
1116 * Intel 64 and IA-32 Architectures Software Developer's Manual
1117 * Volume 3C: System Programming Guide, Part 3
1118 * Order Number 326019
1119 * January 2013
1120 *
1121 * Table 35-4, 35-5
1122 *
1123 * For now it has only been tested with 06_1CH.
1124 */
1125 static const msr_entry_t model6_atom_global_msrs[] = {
1126 { 0x0000, "IA32_P5_MC_ADDR" },
1127 { 0x0001, "IA32_P5_MC_TYPE" },
1128 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
1129 { 0x0017, "IA32_PLATFORM_ID" },
1130 { 0x002a, "MSR_EBC_HARD_POWERON" },
1131 { 0x00cd, "MSR_FSB_FREQ" },
1132 { 0x00fe, "IA32_MTRRCAP" },
1133 { 0x011e, "MSR_BBL_CR_CTL3" },
1134 { 0x0198, "IA32_PERF_STATUS" },
1135 { 0x019d, "MSR_THERM2_CTL" },
1136 { 0x0200, "IA32_MTRR_PHYSBASE0" },
1137 { 0x0201, "IA32_MTRR_PHYSMASK0" },
1138 { 0x0202, "IA32_MTRR_PHYSBASE1" },
1139 { 0x0203, "IA32_MTRR_PHYSMASK1" },
1140 { 0x0204, "IA32_MTRR_PHYSBASE2" },
1141 { 0x0205, "IA32_MTRR_PHYSMASK2" },
1142 { 0x0206, "IA32_MTRR_PHYSBASE3" },
1143 { 0x0207, "IA32_MTRR_PHYSMASK3" },
1144 { 0x0208, "IA32_MTRR_PHYSBASE4" },
1145 { 0x0209, "IA32_MTRR_PHYSMASK4" },
1146 { 0x020a, "IA32_MTRR_PHYSBASE5" },
1147 { 0x020b, "IA32_MTRR_PHYSMASK5" },
1148 { 0x020c, "IA32_MTRR_PHYSBASE6" },
1149 { 0x020d, "IA32_MTRR_PHYSMASK6" },
1150 { 0x020e, "IA32_MTRR_PHYSBASE7" },
1151 { 0x020f, "IA32_MTRR_PHYSMASK7" },
1152 { 0x0250, "IA32_MTRR_FIX64K_00000" },
1153 { 0x0258, "IA32_MTRR_FIX16K_80000" },
1154 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
1155 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
1156 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
1157 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
1158 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
1159 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
1160 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
1161 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
1162 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
1163 { 0x0345, "IA32_PERF_CAPABILITIES" },
1164 { 0x400, "IA32_MC0_CTL" },
1165 { 0x401, "IA32_MC0_STATUS" },
1166 { 0x402, "IA32_MC0_ADDR" },
1167 { 0x404, "IA32_MC1_CTL" },
1168 { 0x405, "IA32_MC1_STATUS" },
1169 { 0x408, "IA32_MC2_CTL" },
1170 { 0x409, "IA32_MC2_STATUS" },
1171 { 0x40a, "IA32_MC2_ADDR" },
1172 { 0x40c, "IA32_MC3_CTL" },
1173 { 0x40d, "IA32_MC3_STATUS" },
1174 { 0x40e, "IA32_MC3_ADDR" },
1175 { 0x410, "IA32_MC4_CTL" },
1176 { 0x411, "IA32_MC4_STATUS" },
1177 { 0x412, "IA32_MC4_ADDR" },
1178 /*
1179 * Only 06_27C has the following MSRs
1180 */
1181 /*
1182 { 0x03f8, "MSR_PKG_C2_RESIDENCY" },
1183 { 0x03f9, "MSR_PKG_C4_RESIDENCY" },
1184 { 0x03fa, "MSR_PKG_C6_RESIDENCY" },
1185 */
1186 };
1187
Elyes HAOUAS94501502016-10-19 17:59:10 +0200[diff] [blame]1188 static const msr_entry_t model6_atom_per_core_msrs[] = {
1189 { 0x0006, "IA32_MONITOR_FILTER_SIZE" },
1190 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
1191 { 0x001b, "IA32_APIC_BASE" },
1192 { 0x003a, "IA32_FEATURE_CONTROL" },
1193 { 0x0040, "MSR_LASTBRANCH_0_FROM_IP" },
1194 { 0x0041, "MSR_LASTBRANCH_1_FROM_IP" },
1195 { 0x0042, "MSR_LASTBRANCH_2_FROM_IP" },
1196 { 0x0043, "MSR_LASTBRANCH_3_FROM_IP" },
1197 { 0x0044, "MSR_LASTBRANCH_4_FROM_IP" },
1198 { 0x0045, "MSR_LASTBRANCH_5_FROM_IP" },
1199 { 0x0046, "MSR_LASTBRANCH_6_FROM_IP" },
1200 { 0x0047, "MSR_LASTBRANCH_7_FROM_IP" },
1201 { 0x0060, "MSR_LASTBRANCH_0_TO_IP" },
1202 { 0x0061, "MSR_LASTBRANCH_1_TO_IP" },
1203 { 0x0062, "MSR_LASTBRANCH_2_TO_IP" },
1204 { 0x0063, "MSR_LASTBRANCH_3_TO_IP" },
1205 { 0x0064, "MSR_LASTBRANCH_4_TO_IP" },
1206 { 0x0065, "MSR_LASTBRANCH_5_TO_IP" },
1207 { 0x0066, "MSR_LASTBRANCH_6_TO_IP" },
1208 { 0x0067, "MSR_LASTBRANCH_7_TO_IP" },
1209 /* Write register */
1210 /*
1211 { 0x0079, "IA32_BIOS_UPDT_TRIG" },
1212 */
1213 { 0x008b, "IA32_BIOS_SIGN_ID" },
1214 { 0x00c1, "IA32_PMC0" },
1215 { 0x00c2, "IA32_PMC1" },
1216 { 0x00e7, "IA32_MPERF" },
1217 { 0x00e8, "IA32_APERF" },
1218 { 0x0174, "IA32_SYSENTER_CS" },
1219 { 0x0175, "IA32_SYSENTER_ESP" },
1220 { 0x0176, "IA32_SYSENTER_EIP" },
1221 { 0x017a, "IA32_MCG_STATUS" },
1222 { 0x0186, "IA32_PERF_EVNTSEL0" },
1223 { 0x0187, "IA32_PERF_EVNTSEL1" },
1224 { 0x0199, "IA32_PERF_CONTROL" },
1225 { 0x019a, "IA32_CLOCK_MODULATION" },
1226 { 0x019b, "IA32_THERM_INTERRUPT" },
1227 { 0x019c, "IA32_THERM_STATUS" },
1228 { 0x01a0, "IA32_MISC_ENABLES" },
1229 { 0x01c9, "MSR_LASTBRANCH_TOS" },
1230 { 0x01d9, "IA32_DEBUGCTL" },
1231 { 0x01dd, "MSR_LER_FROM_LIP" },
1232 { 0x01de, "MSR_LER_TO_LIP" },
1233 { 0x0277, "IA32_PAT" },
1234 { 0x0309, "IA32_FIXED_CTR0" },
1235 { 0x030a, "IA32_FIXED_CTR1" },
1236 { 0x030b, "IA32_FIXED_CTR2" },
1237 { 0x038d, "IA32_FIXED_CTR_CTRL" },
1238 { 0x038e, "IA32_PERF_GLOBAL_STATUS" },
1239 { 0x038f, "IA32_PERF_GLOBAL_CTRL" },
1240 { 0x0390, "IA32_PERF_GLOBAL_OVF_CTRL" },
1241 { 0x03f1, "MSR_PEBS_ENABLE" },
1242 { 0x0480, "IA32_VMX_BASIC" },
1243 { 0x0481, "IA32_VMX_PINBASED_CTLS" },
1244 { 0x0482, "IA32_VMX_PROCBASED_CTLS" },
1245 { 0x0483, "IA32_VMX_EXIT_CTLS" },
1246 { 0x0484, "IA32_VMX_ENTRY_CTLS" },
1247 { 0x0485, "IA32_VMX_MISC" },
1248 { 0x0486, "IA32_VMX_CR0_FIXED0" },
1249 { 0x0487, "IA32_VMX_CR0_FIXED1" },
1250 { 0x0488, "IA32_VMX_CR4_FIXED0" },
1251 { 0x0489, "IA32_VMX_CR4_FIXED1" },
1252 { 0x048a, "IA32_VMX_VMCS_ENUM" },
1253 { 0x048b, "IA32_VMX_PROCBASED_CTLS2" },
1254 { 0x0600, "IA32_DS_AREA" },
1255 };
Olivier Langlois70f39872013-01-25 00:49:46 -0500[diff] [blame]1256
Vladimir Serbinenkoe4e8e092013-03-31 13:51:37 +0200[diff] [blame]1257 static const msr_entry_t model20650_global_msrs[] = {
1258 { 0x0000, "IA32_P5_MC_ADDR" },
1259 { 0x0001, "IA32_P5_MC_TYPE" },
1260 { 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" },
1261 { 0x0017, "IA32_PLATFORM_ID" },
1262 { 0x002a, "MSR_EBC_HARD_POWERON" },
1263// WRITE ONLY { 0x0079, "IA32_BIOS_UPDT_TRIG" },
1264 { 0x00ce, "IA32_MSR_PLATFORM_INFO" },
1265 { 0x00e2, "IA32_MSR_PMG_CST_CONFIG" },
1266 { 0x019c, "IA32_THERM_STATUS" },
1267 { 0x019d, "MSR_THERM2_CTL" },
1268 { 0x01a0, "IA32_MISC_ENABLE" },
1269 { 0x0200, "IA32_MTRR_PHYSBASE0" },
1270 { 0x0201, "IA32_MTRR_PHYSMASK0" },
1271 { 0x0202, "IA32_MTRR_PHYSBASE1" },
1272 { 0x0203, "IA32_MTRR_PHYSMASK1" },
1273 { 0x0204, "IA32_MTRR_PHYSBASE2" },
1274 { 0x0205, "IA32_MTRR_PHYSMASK2" },
1275 { 0x0206, "IA32_MTRR_PHYSBASE3" },
1276 { 0x0207, "IA32_MTRR_PHYSMASK3" },
1277 { 0x0208, "IA32_MTRR_PHYSBASE4" },
1278 { 0x0209, "IA32_MTRR_PHYSMASK4" },
1279 { 0x020a, "IA32_MTRR_PHYSBASE5" },
1280 { 0x020b, "IA32_MTRR_PHYSMASK5" },
1281 { 0x020c, "IA32_MTRR_PHYSBASE6" },
1282 { 0x020d, "IA32_MTRR_PHYSMASK6" },
1283 { 0x020e, "IA32_MTRR_PHYSBASE7" },
1284 { 0x020f, "IA32_MTRR_PHYSMASK7" },
1285 { 0x0250, "IA32_MTRR_FIX64K_00000" },
1286 { 0x0258, "IA32_MTRR_FIX16K_80000" },
1287 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
1288 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
1289 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
1290 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
1291 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
1292 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
1293 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
1294 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
1295 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
1296 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
1297 { 0x0300, "MSR_BPU_COUNTER0" },
1298 { 0x0301, "MSR_BPU_COUNTER1" },
1299 /* Skipped through 0x3ff for now*/
1300
1301 /* All MCX_ADDR AND MCX_MISC MSRs depend on a bit being
1302 * set in MCX_STATUS */
1303 { 0x400, "IA32_MC0_CTL" },
1304 { 0x401, "IA32_MC0_STATUS" },
1305 { 0x402, "IA32_MC0_ADDR" },
1306 { 0x403, "IA32_MC0_MISC" },
1307 { 0x404, "IA32_MC1_CTL" },
1308 { 0x405, "IA32_MC1_STATUS" },
1309 { 0x406, "IA32_MC1_ADDR" },
1310 { 0x407, "IA32_MC1_MISC" },
1311 { 0x408, "IA32_MC2_CTL" },
1312 { 0x409, "IA32_MC2_STATUS" },
1313 { 0x40a, "IA32_MC2_ADDR" },
1314 { 0x40c, "IA32_MC3_CTL" },
1315 { 0x40d, "IA32_MC3_STATUS" },
1316 { 0x40e, "IA32_MC3_ADDR" },
1317 { 0x410, "IA32_MC4_CTL" },
1318 { 0x411, "IA32_MC4_STATUS" },
1319 };
1320
1321 static const msr_entry_t model20650_per_core_msrs[] = {
1322 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
1323 { 0x001b, "IA32_APIC_BASE" },
1324 { 0x003a, "IA32_FEATURE_CONTROL" },
1325 { 0x008b, "IA32_BIOS_SIGN_ID" },
1326 { 0x009b, "IA32_SMM_MONITOR_CTL" },
1327 { 0x00e4, "IA32_PMG_IO_CAPTURE_BASE" },
1328 { 0x00fe, "IA32_MTRRCAP" },
1329 { 0x0174, "IA32_SYSENTER_CS" },
1330 { 0x0175, "IA32_SYSENTER_ESP" },
1331 { 0x0176, "IA32_SYSENTER_EIP" },
1332 { 0x0179, "IA32_MCG_CAP" },
1333 { 0x017a, "IA32_MCG_STATUS" },
1334 { 0x0186, "MSR_MCG_RBP" },
1335 { 0x0187, "MSR_MCG_RSP" },
1336 { 0x0188, "MSR_MCG_RFLAGS" },
1337 { 0x0189, "MSR_MCG_RIP" },
1338 { 0x0194, "MSR_MCG_R12" },
1339 { 0x0198, "IA32_PERF_STATUS" },
1340 { 0x0199, "IA32_PERF_CTL" },
1341 { 0x019a, "IA32_CLOCK_MODULATION" },
1342 { 0x019b, "IA32_THERM_INTERRUPT" },
1343 { 0x01a0, "IA32_MISC_ENABLE" }, // Bit 34 is Core Specific
1344 { 0x01aa, "IA32_MISC_PWR_MGMT" },
1345 { 0x01d9, "MSR_DEBUGCTLA" },
1346 { 0x01fc, "MSR_POWER_CTL" },
1347 { 0x0277, "IA32_PAT" },
1348 /** Virtualization
1349 { 0x480, "IA32_VMX_BASIC" },
1350 through
1351 { 0x48b, "IA32_VMX_PROCBASED_CTLS2" },
1352 Not implemented in my CPU
1353 */
1354 { 0x0600, "IA32_DS_AREA" },
1355 /* 0x0680 - 0x06cf Branch Records Skipped */
1356
1357 { 0x3a, "IA32_FEATURE_CONTROL" },
1358 { 0x13c, "MSR_FEATURE_CONFIG" },
1359 { 0x194, "MSR_FLEX_RATIO" },
1360 { 0x1a0, "IA32_MISC_ENABLE" },
1361 { 0x1a2, "MSR_TEMPERATURE_TARGET" },
1362 { 0x199, "IA32_PERF_CTL" },
1363 { 0x19b, "IA32_THERM_INTERRUPT" },
1364 { 0x401, "IA32_MC0_STATUS" },
1365 { 0x2e, "MSR_PIC_MSG_CONTROL" },
1366 { 0xce, "MSR_PLATFORM_INFO" },
1367 { 0xe2, "MSR_PMG_CST_CONFIG_CONTROL" },
1368 { 0xe4, "MSR_PMG_IO_CAPTURE_BASE" },
1369 { 0x1aa, "MSR_MISC_PWR_MGMT" },
1370 { 0x1ad, "MSR_TURBO_RATIO_LIMIT" },
1371 { 0x1fc, "MSR_POWER_CTL" },
1372 };
1373
Martin Roth51dde6f2014-12-07 22:11:54 -0700[diff] [blame]1374/*
1375 * The following two tables are the Silvermont registers listed in Table 35-6
Martin Roth0cd338e2016-07-29 14:07:30 -0600[diff] [blame]1376 * Intel® 64 and IA-32 Architectures Software Developer's Manual
Martin Roth51dde6f2014-12-07 22:11:54 -0700[diff] [blame]1377 * September 2014
1378 * Vol. 3C 35-59
1379 */
1380 static const msr_entry_t silvermont_per_core_msrs[] = {
1381 /*
1382 * Per core MSRs in Intel Processors Based on the Silvermont Microarchitecture
1383 * These are MSRs marked as "core"
1384 *
1385 */
1386 { 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" },
1387 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
1388 { 0x001b, "IA32_APIC_BASE" },
1389 { 0x0034, "MSR_SMI_COUNT" },
1390 { 0x003a, "IA32_FEATURE_CONTROL" },
1391 { 0x0040, "MSR_LASTBRANCH_0_FROM_IP" },
1392 { 0x0041, "MSR_LASTBRANCH_1_FROM_IP" },
1393 { 0x0042, "MSR_LASTBRANCH_2_FROM_IP" },
1394 { 0x0043, "MSR_LASTBRANCH_3_FROM_IP" },
1395 { 0x0044, "MSR_LASTBRANCH_4_FROM_IP" },
1396 { 0x0045, "MSR_LASTBRANCH_5_FROM_IP" },
1397 { 0x0046, "MSR_LASTBRANCH_6_FROM_IP" },
1398 { 0x0047, "MSR_LASTBRANCH_7_FROM_IP" },
1399 { 0x0060, "MSR_LASTBRANCH_0_TO_IP" },
1400 { 0x0061, "MSR_LASTBRANCH_1_TO_IP" },
1401 { 0x0062, "MSR_LASTBRANCH_2_TO_IP" },
1402 { 0x0063, "MSR_LASTBRANCH_3_TO_IP" },
1403 { 0x0064, "MSR_LASTBRANCH_4_TO_IP" },
1404 { 0x0065, "MSR_LASTBRANCH_5_TO_IP" },
1405 { 0x0066, "MSR_LASTBRANCH_6_TO_IP" },
1406 { 0x0067, "MSR_LASTBRANCH_7_TO_IP" },
1407 /* Write register
1408 { 0x0079, "IA32_BIOS_UPDT_TRIG" },
1409 */
1410 { 0x008b, "IA32_BIOS_SIGN_ID" },
1411 { 0x00c1, "IA32_PMC0" },
1412 { 0x00c2, "IA32_PMC1" },
1413 { 0x00e7, "IA32_MPERF" },
1414 { 0x00e8, "IA32_APERF" },
1415 { 0x00fe, "IA32_MTRRCAP" },
1416 { 0x0174, "IA32_SYSENTER_CS" },
1417 { 0x0175, "IA32_SYSENTER_ESP" },
1418 { 0x0176, "IA32_SYSENTER_EIP" },
1419 { 0x0179, "IA32_MCG_CAP" },
1420 { 0x017a, "IA32_MCG_STATUS" },
1421 { 0x0186, "IA32_PERF_EVNTSEL0" },
1422 { 0x0187, "IA32_PERF_EVNTSEL1" },
1423 { 0x0199, "IA32_PERF_CONTROL" },
1424 { 0x019a, "IA32_CLOCK_MODULATION" },
1425 { 0x019b, "IA32_THERM_INTERRUPT" },
1426 { 0x019c, "IA32_THERM_STATUS" },
1427 { 0x01a0, "IA32_MISC_ENABLES" },
1428 { 0x01b0, "IA32_ENERGY_PERF_BIAS" },
1429 { 0x01c9, "MSR_LASTBRANCH_TOS" },
1430 { 0x01d9, "IA32_DEBUGCTL" },
1431 { 0x01dd, "MSR_LER_FROM_LIP" },
1432 { 0x01de, "MSR_LER_TO_LIP" },
1433 { 0x01f2, "IA32_SMRR_PHYSBASE" },
1434 { 0x01f3, "IA32_SMRR_PHYSMASK" },
1435 { 0x0200, "IA32_MTRR_PHYSBASE0" },
1436 { 0x0201, "IA32_MTRR_PHYSMASK0" },
1437 { 0x0202, "IA32_MTRR_PHYSBASE1" },
1438 { 0x0203, "IA32_MTRR_PHYSMASK1" },
1439 { 0x0204, "IA32_MTRR_PHYSBASE2" },
1440 { 0x0205, "IA32_MTRR_PHYSMASK2" },
1441 { 0x0206, "IA32_MTRR_PHYSBASE3" },
1442 { 0x0207, "IA32_MTRR_PHYSMASK3" },
1443 { 0x0208, "IA32_MTRR_PHYSBASE4" },
1444 { 0x0209, "IA32_MTRR_PHYSMASK4" },
1445 { 0x020a, "IA32_MTRR_PHYSBASE5" },
1446 { 0x020b, "IA32_MTRR_PHYSMASK5" },
1447 { 0x020c, "IA32_MTRR_PHYSBASE6" },
1448 { 0x020d, "IA32_MTRR_PHYSMASK6" },
1449 { 0x020e, "IA32_MTRR_PHYSBASE7" },
1450 { 0x020f, "IA32_MTRR_PHYSMASK7" },
1451 { 0x0250, "IA32_MTRR_FIX64K_00000" },
1452 { 0x0258, "IA32_MTRR_FIX16K_80000" },
1453 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
1454 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
1455 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
1456 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
1457 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
1458 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
1459 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
1460 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
1461 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
1462 { 0x0277, "IA32_PAT" },
1463 { 0x02FF, "IA32_MTRR_DEF_TYPE" },
1464 { 0x0309, "IA32_FIXED_CTR0" },
1465 { 0x030a, "IA32_FIXED_CTR1" },
1466 { 0x030b, "IA32_FIXED_CTR2" },
1467 { 0x0345, "IA32_PERF_CAPABILITIES" },
1468 { 0x038d, "IA32_FIXED_CTR_CTRL" },
1469 { 0x038e, "IA32_PERF_GLOBAL_STATUS" },
1470 { 0x038f, "IA32_PERF_GLOBAL_CTRL" },
1471 { 0x0390, "IA32_PERF_GLOBAL_OVF_CTRL" },
1472 { 0x03f1, "MSR_PEBS_ENABLE" },
1473 { 0x03fd, "MSR_CORE_C6_RESIDENCY" },
1474 { 0x40c, "IA32_MC3_CTL" },
1475 { 0x40d, "IA32_MC3_STATUS" },
1476 { 0x40e, "IA32_MC3_ADDR" },
1477 { 0x410, "IA32_MC4_CTL" },
1478 { 0x411, "IA32_MC4_STATUS" },
1479 { 0x412, "IA32_MC4_ADDR" },
1480 { 0x0480, "IA32_VMX_BASIC" },
1481 { 0x0481, "IA32_VMX_PINBASED_CTLS" },
1482 { 0x0482, "IA32_VMX_PROCBASED_CTLS" },
1483 { 0x0483, "IA32_VMX_EXIT_CTLS" },
1484 { 0x0484, "IA32_VMX_ENTRY_CTLS" },
1485 { 0x0485, "IA32_VMX_MISC" },
1486 { 0x0486, "IA32_VMX_CR0_FIXED0" },
1487 { 0x0487, "IA32_VMX_CR0_FIXED1" },
1488 { 0x0488, "IA32_VMX_CR4_FIXED0" },
1489 { 0x0489, "IA32_VMX_CR4_FIXED1" },
1490 { 0x048a, "IA32_VMX_VMCS_ENUM" },
1491 { 0x048b, "IA32_VMX_PROCBASED_CTLS2" },
1492 { 0x048c, "IA32_VMX_EPT_VPID_ENUM" },
1493 { 0x048d, "IA32_VMX_TRUE_PINBASED_CTLS" },
1494 { 0x048e, "IA32_VMX_TRUE_PROCBASED_CTLS" },
1495 { 0x048f, "IA32_VMX_TRUE_EXIT_CTLS" },
1496 { 0x0490, "IA32_VMX_TRUE_ENTRY_CTLS" },
1497 { 0x0491, "IA32_VMX_FMFUNC" },
1498 { 0x04c1, "IA32_A_PMC0" },
1499 { 0x04c2, "IA32_A_PMC1" },
1500 { 0x0600, "IA32_DS_AREA" },
1501 { 0x0660, "MSR_CORE_C1_RESIDENCY" },
1502 { 0x06e0, "IA32_TSC_DEADLINE" },
1503 };
1504
1505 static const msr_entry_t silvermont_global_msrs[] = {
1506 /*
1507 * Common MSRs in Intel Processors Based on the Silvermont Microarchitecture
1508 * These are MSRs marked as "shared" or "package"
1509 */
1510 { 0x0000, "IA32_P5_MC_ADDR" },
1511 { 0x0001, "IA32_P5_MC_TYPE" },
1512 { 0x0017, "IA32_PLATFORM_ID" },
1513 { 0x002a, "MSR_EBC_HARD_POWERON" },
1514 { 0x00cd, "MSR_FSB_FREQ" },
1515 { 0x00e2, "MSR_PKG_CST_CONFIG_CONTROL" },
1516 { 0x00e4, "MSR_PMG_IO_CAPTURE_BASE" },
1517 { 0x011e, "BBL_CR_CTL3" },
1518 { 0x0198, "IA32_PERF_STATUS" },
1519 { 0x01A2, "MSR_TEMPERATURE_TARGET" },
1520 { 0x01A6, "MSR_OFFCORE_RSP_0" },
1521 { 0x01A7, "MSR_OFFCORE_RSP_1" },
1522 { 0x01AD, "MSR_TURBO_RATIO_LIMIT" },
1523 { 0x03fa, "MSR_PKG_C6_RESIDENCY" },
1524 { 0x400, "IA32_MC0_CTL" },
1525 { 0x401, "IA32_MC0_STATUS" },
1526 { 0x402, "IA32_MC0_ADDR" },
1527 { 0x404, "IA32_MC1_CTL" },
1528 { 0x405, "IA32_MC1_STATUS" },
1529 { 0x408, "IA32_MC2_CTL" },
1530 { 0x409, "IA32_MC2_STATUS" },
1531 { 0x40a, "IA32_MC2_ADDR" },
1532 { 0x414, "MSR_MC5_CTL" },
1533 { 0x415, "MSR_MC5_STATUS" },
1534 { 0x416, "MSR_MC5_ADDR" },
1535 };
1536
Christian Walter9a8c5e72019-05-06 17:50:57 +0200[diff] [blame]1537/*
1538 * Intel 64 and IA-32 Architectures Software Developers Manual Conbined Volumes
1539 * Page 4668
1540 *
1541 * The following two tables are for the Kaby Lake processors
1542 * 06_9EH.
1543 *
1544 */
1545
1546 static const msr_entry_t model96ex_global_msrs[] = {
Maxim Polyakov3e7ff292019-10-08 12:29:00 +0300[diff] [blame]1547 { 0x0017, "IA32_PLATFORM_ID"},
Christian Walter9a8c5e72019-05-06 17:50:57 +0200[diff] [blame]1548 { 0x0080, "MSR_TRACE_HUB_STH_ACPIBAR_BASE"},
1549 { 0x00CE, "MSR_PLATFORM_INFO"},
1550 { 0x0198, "IA32_PERF_STATUS"},
1551 { 0x01A2, "MSR_TEMPERATURE_TARGET"},
1552 { 0x01AD, "MSR_TURBO_RATIO_LIMIT"},
1553 { 0x0284, "IA32_MC4_CTL2"},
1554 { 0x02F4, "MSR_UNCORE_PRMRR_PHYS_BASE"},
1555 { 0x02F5, "MSR_UNCORE_PRMRR_PHYS_MASK"},
1556 { 0x0394, "MSR_UNC_PERF_FIXED_CTRL"},
1557 { 0x0395, "MSR_UNC_PERF_FIXED_CTR"},
1558 { 0x060A, "MSR_PKGC3_IRTL"},
1559 { 0x060B, "MSR_PKGC6_IRTL"},
1560 { 0x060D, "MSR_PKG_C2_RESIDENCY"},
1561 { 0x0610, "MSR_PKG_POWER_LIMIT"},
1562 { 0x0614, "MSR_PKG_POWER_INFO"},
1563 { 0x0620, "MSR_RING_RATIO_LIMIT"},
1564 { 0x0638, "MSR_PP0_POWER_LIMIT"},
1565 { 0x064F, "MSR_CORE_PERF_LIMIT_REASONS"},
1566 { 0x0652, "MSR_PKG_HDC_CONFIG"},
1567 { 0x065C, "MSR_PLATFORM_POWER_LIMIT"},
1568 { 0x06B0, "MSR_GRAPHICS_PERF_LIMIT_REASONS"},
1569 { 0x06B1, "MSR_RING_PERF_LIMIT_REASONS"},
1570 { 0x0770, "IA32_PM_ENABLE"},
1571 { 0x0DB0, "IA32_PKG_HDC_CTL"},
1572 { 0x03B0, "MSR_UNC_ARB_PERFCTR0"},
1573 { 0x03B1, "MSR_UNC_ARB_PERFCTR1"},
1574 { 0x03B2, "MSR_UNC_ARB_PERFEVTSEL0"},
1575 { 0x03B3, "MSR_UNC_ARB_PERFEVTSEL1"},
1576 { 0x0700, "MSR_UNC_CBO_0_PERFCTR0"},
1577 { 0x0701, "MSR_UNC_CBO_0_PERFCTR1"},
1578 { 0x0706, "MSR_UNC_CBO_0_PERFEVTSEL0"},
1579 { 0x0707, "MSR_UNC_CBO_0_PERFEVTSEL1"},
1580 { 0x0710, "MSR_UNC_CBO_1_PERFCTR0"},
1581 { 0x0711, "MSR_UNC_CBO_1_PERFCTR1"},
1582 { 0x0716, "MSR_UNC_CBO_1_PERFEVTSEL0"},
1583 { 0x0717, "MSR_UNC_CBO_1_PERFEVTSEL1"},
1584 { 0x0720, "MSR_UNC_CBO_2_PERFCTR0"},
1585 { 0x0721, "MSR_UNC_CBO_2_PERFCTR1"},
1586 { 0x0726, "MSR_UNC_CBO_2_PERFEVTSEL0"},
1587 { 0x0727, "MSR_UNC_CBO_2_PERFEVTSEL1"},
1588 { 0x0730, "MSR_UNC_CBO_3_PERFCTR0"},
1589 { 0x0731, "MSR_UNC_CBO_3_PERFCTR1"},
1590 { 0x0736, "MSR_UNC_CBO_3_PERFEVTSEL0"},
1591 { 0x0737, "MSR_UNC_CBO_3_PERFEVTSEL1"},
1592 { 0x0E01, "MSR_UNC_PERF_GLOBAL_CTRL"},
1593 { 0x0E02, "MSR_UNC_PERF_GLOBAL_STATUS"},
1594 };
1595
1596 static const msr_entry_t model96ex_per_core_msrs[] = {
1597 /* Per core MSRs for Sandy Bridge and above */
1598 { 0x0000, "IA32_P5_MC_ADDR"},
1599 { 0x0001, "IA32_P5_MC_TYPE"},
1600 { 0x0006, "IA32_MONITOR_FILTER_SIZE"},
1601 { 0x0010, "IA32_TIME_STAMP_COUNTER"},
1602 { 0x001B, "IA32_APIC_BASE"},
1603 { 0x0034, "MSR_SMI_COUNT"},
1604 { 0x003A, "IA32_FEATURE_CONTROL"},
1605 { 0x008B, "IA32_BIOS_SIGN_ID"},
1606 { 0x00C1, "IA32_PMC0" },
1607 { 0x00C2, "IA32_PMC1" },
1608 { 0x00C3, "IA32_PMC2" },
1609 { 0x00C4, "IA32_PMC3" },
1610 { 0x00E2, "MSR_PKG_CST_CONFIG_CONTROL" },
1611 { 0x00E4, "MSR_PMG_IO_CAPTURE_BASE"},
1612 { 0x00E7, "IA32_MPERF"},
1613 { 0x00E8, "IA32_APERF"},
1614 { 0x00FE, "IA32_MTRRCAP"},
1615 { 0x013C, "MSR_FEATURE_CONFIG"},
1616 { 0x0174, "IA32_SYSENTER_CS"},
1617 { 0x0175, "IA32_SYSENTER_ESP"},
1618 { 0x0176, "IA32_SYSENTER_EIP"},
1619 { 0x0179, "IA32_MCG_CAP"},
1620 { 0x017A, "IA32_MCG_STATUS"},
1621 { 0x0186, "IA32_PERFEVTSEL0"},
1622 { 0x0187, "IA32_PERFEVTSEL1"},
1623 { 0x0188, "IA32_PERFEVTSEL2"},
1624 { 0x0189, "IA32_PERFEVTSEL3"},
1625 { 0x0199, "IA32_PERF_CTL"},
1626 { 0x019A, "IA32_CLOCK_MODULATION"},
1627 { 0x019B, "IA32_THERM_INTERRUPT"},
1628 { 0x019C, "IA32_THERM_STATUS"},
1629 { 0x01A0, "IA32_MISC_ENABLE"},
1630 { 0x01A4, "IA32_MISC_FEATURE_CONTROL"},
1631 { 0x01A6, "MSR_OFFCORE_RSP_0"},
1632 { 0x01A7, "MSR_OFFCORE_RSP_1"},
1633 { 0x01C8, "MSR_LBR_SELECT"},
1634 { 0x01C9, "MSR_LASTBRANCH_TOS"},
1635 { 0x01D9, "IA32_DEBUGCTL"},
1636 { 0x01DD, "MSR_LER_FROM_LIP"},
1637 { 0x01DE, "MSR_LER_TO_LIP"},
1638 { 0x01F2, "IA32_SMRR_PHYSBASE"},
1639 { 0x01F3, "IA32_SMRR_PHYSMASK"},
1640 { 0x01F4, "MSR_PRMRR_PHYS_BASE"},
1641 { 0x01F5, "MSR_PRMRR_PHYS_MASK"},
Christian Walter9a8c5e72019-05-06 17:50:57 +0200[diff] [blame]1642 { 0x01FB, "MSR_PRMRR_VALID_CONFIG"},
1643 { 0x01FC, "MSR_POWER_CTL"},
1644 { 0x0200, "IA32_MTRR_PHYSBASE0"},
1645 { 0x0201, "IA32_MTRR_PHYSBASE0"},
1646 { 0x0202, "IA32_MTRR_PHYSBASE1"},
1647 { 0x0203, "IA32_MTRR_PHYSBASE1"},
1648 { 0x0204, "IA32_MTRR_PHYSBASE2"},
1649 { 0x0205, "IA32_MTRR_PHYSBASE2"},
1650 { 0x0206, "IA32_MTRR_PHYSBASE3"},
1651 { 0x0207, "IA32_MTRR_PHYSBASE3"},
1652 { 0x0208, "IA32_MTRR_PHYSBASE4"},
1653 { 0x0209, "IA32_MTRR_PHYSBASE4"},
1654 { 0x020A, "IA32_MTRR_PHYSBASE5"},
1655 { 0x020B, "IA32_MTRR_PHYSBASE5"},
1656 { 0x020C, "IA32_MTRR_PHYSBASE6"},
1657 { 0x020D, "IA32_MTRR_PHYSBASE6"},
1658 { 0x020E, "IA32_MTRR_PHYSBASE7"},
1659 { 0x020F, "IA32_MTRR_PHYSBASE7"},
1660 { 0x0210, "IA32_MTRR_PHYSBASE8"},
1661 { 0x0211, "IA32_MTRR_PHYSBASE8"},
1662 { 0x0212, "IA32_MTRR_PHYSBASE9"},
1663 { 0x0213, "IA32_MTRR_PHYSBASE9"},
1664 { 0x0250, "IA32_MTRR_FIX64K_00000"},
1665 { 0x0258, "IA32_MTRR_FIX16K_80000"},
1666 { 0x0259, "IA32_MTRR_FIX16K_A0000"},
1667 { 0x0268, "IA32_MTRR_FIX4K_C0000"},
1668 { 0x0269, "IA32_MTRR_FIX4K_C8000"},
1669 { 0x026A, "IA32_MTRR_FIX4K_D0000"},
1670 { 0x026B, "IA32_MTRR_FIX4K_D8000"},
1671 { 0x026C, "IA32_MTRR_FIX4K_E0000"},
1672 { 0x026D, "IA32_MTRR_FIX4K_E8000"},
1673 { 0x026E, "IA32_MTRR_FIX4K_F0000"},
1674 { 0x026F, "IA32_MTRR_FIX4K_F8000"},
1675 { 0x0277, "IA32_PAT"},
1676 { 0x0280, "IA32_MC0_CTL2"},
1677 { 0x0281, "IA32_MC1_CTL2"},
1678 { 0x0282, "IA32_MC2_CTL2"},
1679 { 0x0283, "IA32_MC3_CTL2"},
1680 { 0x02FF, "IA32_MTRR_DEF_TYPE"},
1681 { 0x0309, "IA32_FIXED_CTR0"},
1682 { 0x030A, "IA32_FIXED_CTR1"},
1683 { 0x030B, "IA32_FIXED_CTR2"},
1684 { 0x0345, "IA32_PERF_CAPABILITIES"},
1685 { 0x038D, "IA32_FIXED_CTR_CTRL"},
1686 { 0x038E, "IA32_PERF_GLOBAL_STATUS"},
1687 { 0x038F, "IA32_PERF_GLOBAL_CTRL"},
1688 { 0x0390, "IA32_PERF_GLOBAL_STATUS_RESET"},
1689 { 0x0391, "IA32_PERF_GLOBAL_STATUS_SET"},
1690 { 0x03F1, "MSR_PEBS_ENABLE"},
1691 { 0x03F6, "MSR_PEBS_LD_LAT"},
1692 { 0x03F7, "MSR_PEBS_FRONTEND"},
1693 { 0x03FC, "MSR_CORE_C3_RESIDENCY"},
1694 { 0x03FD, "MSR_CORE_C6_RESIDENCY"},
1695 { 0x03FE, "MSR_CORE_C7_RESIDENCY"},
1696 { 0x0400, "IA32_MC0_CTL" },
1697 { 0x0401, "IA32_MC0_STATUS" },
1698 { 0x0402, "IA32_MC0_ADDR" },
1699 { 0x0403, "IA32_MC0_MISC" },
1700 { 0x0404, "IA32_MC1_CTL" },
1701 { 0x0405, "IA32_MC1_STATUS" },
1702 { 0x0406, "IA32_MC1_ADDR" },
1703 { 0x0407, "IA32_MC1_MISC" },
1704 { 0x0408, "IA32_MC2_CTL" },
1705 { 0x0409, "IA32_MC2_STATUS" },
1706 { 0x040a, "IA32_MC2_ADDR" },
1707 { 0x040c, "IA32_MC3_CTL" },
1708 { 0x040d, "IA32_MC3_STATUS" },
1709 { 0x040e, "IA32_MC3_ADDR" },
1710 { 0x0410, "IA32_MC4_CTL" },
1711 { 0x0411, "IA32_MC4_STATUS" },
1712 { 0x0480, "IA32_VMX_BASIC" },
1713 { 0x0481, "IA32_VMX_PINBASED_CTLS" },
1714 { 0x0482, "IA32_VMX_PROCBASED_CTLS" },
1715 { 0x0483, "IA32_VMX_EXIT_CTLS" },
1716 { 0x0484, "IA32_VMX_ENTRY_CTLS" },
1717 { 0x0485, "IA32_VMX_MISC" },
1718 { 0x0486, "IA32_VMX_CR0_FIXED0" },
1719 { 0x0487, "IA32_VMX_CR0_FIXED1" },
1720 { 0x0488, "IA32_VMX_CR4_FIXED0" },
1721 { 0x0489, "IA32_VMX_CR4_FIXED1" },
1722 { 0x048a, "IA32_VMX_VMCS_ENUM" },
1723 { 0x048b, "IA32_VMX_PROCBASED_CTLS2" },
1724 { 0x048c, "IA32_VMX_EPT_VPID_ENUM" },
1725 { 0x048d, "IA32_VMX_TRUE_PINBASED_CTLS" },
1726 { 0x048e, "IA32_VMX_TRUE_PROCBASED_CTLS" },
1727 { 0x048f, "IA32_VMX_TRUE_EXIT_CTLS" },
1728 { 0x0490, "IA32_VMX_TRUE_ENTRY_CTLS" },
1729 { 0x04C1, "IA32_A_PMC0"},
1730 { 0x04C2, "IA32_A_PMC1"},
1731 { 0x04C3, "IA32_A_PMC2"},
1732 { 0x04C4, "IA32_A_PMC3"},
1733 { 0x0500, "IA32_SGX_SVN_STATUS"},
1734 { 0x0560, "IA32_RTIT_OUTPUT_BASE"},
1735 { 0x0561, "IA32_RTIT_OUTPUT_MASK_PTRS"},
1736 { 0x0570, "IA32_RTIT_CTL"},
1737 { 0x0571, "IA32_RTIT_STATUS"},
1738 { 0x0572, "IA32_RTIT_CR3_MATCH"},
1739 { 0x0580, "IA32_RTIT_ADDR0_A"},
1740 { 0x0581, "IA32_RTIT_ADDR0_B"},
1741 { 0x0582, "IA32_RTIT_ADDR1_A"},
1742 { 0x0583, "IA32_RTIT_ADDR1_B"},
1743 { 0x0600, "IA32_DS_AREA" },
1744 { 0x064E, "MSR_PPERF"},
1745 { 0x0653, "MSR_CORE_HDC_RESIDENCY"},
Christian Walter9a8c5e72019-05-06 17:50:57 +0200[diff] [blame]1746 { 0x0690, "MSR_LASTBRANCH_16_FROM_IP" },
1747 { 0x0691, "MSR_LASTBRANCH_17_FROM_IP" },
1748 { 0x0692, "MSR_LASTBRANCH_18_FROM_IP" },
1749 { 0x0693, "MSR_LASTBRANCH_19_FROM_IP" },
1750 { 0x0694, "MSR_LASTBRANCH_20_FROM_IP" },
1751 { 0x0695, "MSR_LASTBRANCH_21_FROM_IP" },
1752 { 0x0696, "MSR_LASTBRANCH_22_FROM_IP" },
1753 { 0x0697, "MSR_LASTBRANCH_23_FROM_IP" },
1754 { 0x0698, "MSR_LASTBRANCH_24_FROM_IP" },
1755 { 0x0699, "MSR_LASTBRANCH_25_FROM_IP" },
1756 { 0x069A, "MSR_LASTBRANCH_26_FROM_IP" },
1757 { 0x069B, "MSR_LASTBRANCH_27_FROM_IP" },
1758 { 0x069C, "MSR_LASTBRANCH_28_FROM_IP" },
1759 { 0x069D, "MSR_LASTBRANCH_29_FROM_IP" },
1760 { 0x069E, "MSR_LASTBRANCH_30_FROM_IP" },
1761 { 0x069F, "MSR_LASTBRANCH_31_FROM_IP" },
Maxim Polyakov9ebf5312019-10-09 11:16:07 +0300[diff] [blame]1762 { 0x06d0, "MSR_LASTBRANCH_16_TO_IP" },
1763 { 0x06d1, "MSR_LASTBRANCH_17_TO_IP" },
1764 { 0x06d2, "MSR_LASTBRANCH_18_TO_IP" },
1765 { 0x06d3, "MSR_LASTBRANCH_19_TO_IP" },
1766 { 0x06d4, "MSR_LASTBRANCH_20_TO_IP" },
1767 { 0x06d5, "MSR_LASTBRANCH_21_TO_IP" },
1768 { 0x06d6, "MSR_LASTBRANCH_22_TO_IP" },
1769 { 0x06d7, "MSR_LASTBRANCH_23_TO_IP" },
1770 { 0x06d8, "MSR_LASTBRANCH_24_TO_IP" },
1771 { 0x06d9, "MSR_LASTBRANCH_25_TO_IP" },
1772 { 0x06da, "MSR_LASTBRANCH_26_TO_IP" },
1773 { 0x06db, "MSR_LASTBRANCH_27_TO_IP" },
1774 { 0x06dc, "MSR_LASTBRANCH_28_TO_IP" },
1775 { 0x06dd, "MSR_LASTBRANCH_29_TO_IP" },
1776 { 0x06de, "MSR_LASTBRANCH_30_TO_IP" },
1777 { 0x06df, "MSR_LASTBRANCH_31_TO_IP" },
Christian Walter9a8c5e72019-05-06 17:50:57 +0200[diff] [blame]1778 { 0x06E0, "IA32_TSC_DEADLINE"},
1779 { 0x0771, "IA32_HWP_CAPABILITIES"},
1780 { 0x0773, "IA32_HWP_INTERRUPT"},
1781 { 0x0774, "IA32_HWP_REQUEST"},
1782 { 0x0777, "IA32_HWP_STATUS"},
1783 { 0x0D90, "IA32_BNDCFGS"},
1784 { 0x0DA0, "IA32_XSS"},
1785 { 0x0DB1, "IA32_PM_CTL1"},
1786 { 0x0DB2, "IA32_THREAD_STALL"},
1787 { 0x0DC0, "IA32_LBR_INFO_0"},
1788 { 0x0DC1, "IA32_LBR_INFO_1"},
1789 { 0x0DC2, "IA32_LBR_INFO_2"},
1790 { 0x0DC3, "IA32_LBR_INFO_3"},
1791 { 0x0DC4, "IA32_LBR_INFO_4"},
1792 { 0x0DC5, "IA32_LBR_INFO_5"},
1793 { 0x0DC6, "IA32_LBR_INFO_6"},
1794 { 0x0DC7, "IA32_LBR_INFO_7"},
1795 { 0x0DC8, "IA32_LBR_INFO_8"},
1796 { 0x0DC9, "IA32_LBR_INFO_9"},
1797 { 0x0DCA, "IA32_LBR_INFO_10"},
1798 { 0x0DCB, "IA32_LBR_INFO_11"},
1799 { 0x0DCC, "IA32_LBR_INFO_12"},
1800 { 0x0DCD, "IA32_LBR_INFO_13"},
1801 { 0x0DCE, "IA32_LBR_INFO_14"},
1802 { 0x0DCF, "IA32_LBR_INFO_15"},
1803 { 0x0DD0, "IA32_LBR_INFO_16"},
1804 { 0x0DD1, "IA32_LBR_INFO_17"},
1805 { 0x0DD2, "IA32_LBR_INFO_18"},
1806 { 0x0DD3, "IA32_LBR_INFO_19"},
1807 { 0x0DD4, "IA32_LBR_INFO_20"},
1808 { 0x0DD5, "IA32_LBR_INFO_21"},
1809 { 0x0DD6, "IA32_LBR_INFO_22"},
1810 { 0x0DD7, "IA32_LBR_INFO_23"},
1811 { 0x0DD8, "IA32_LBR_INFO_24"},
1812 { 0x0DD9, "IA32_LBR_INFO_25"},
1813 { 0x0DDA, "IA32_LBR_INFO_26"},
1814 { 0x0DDB, "IA32_LBR_INFO_27"},
1815 { 0x0DDC, "IA32_LBR_INFO_28"},
1816 { 0x0DDD, "IA32_LBR_INFO_29"},
1817 { 0x0DDE, "IA32_LBR_INFO_30"},
1818 { 0x0DDF, "IA32_LBR_INFO_31"},
1819 };
1820
Maxim Polyakov9af10bf2019-10-08 17:33:59 +0300[diff] [blame]1821/*
1822 * Intel® 64 and IA-32 Architecture Software Developer’s Manual
1823 * Volume 4: Model-Specific Registers
1824 * Order Number: 335592-070US
1825 * page 2-265 ... 2-286
1826 * page 2-297 ... 2-308
1827 *
1828 * The following two tables are for the Intel(R) Xeon(R) Processor Scalable
1829 * Family based on Skylake microarchitecture, 2nd generation Intel(R) Xeon(R)
1830 * Processor Scalable Family based on Cascade Lake product, and future Cooper
1831 * Lake product
1832 * family 6 model 85 (06_55h)
1833 */
1834 static const msr_entry_t model565x_global_msrs[] = {
1835 { 0x004e, "MSR_PPIN_CTL" },
1836 { 0x004f, "MSR_PPIN" },
1837 { 0x00ce, "MSR_PLATFORM_INFO" },
1838 { 0x0198, "IA32_PERF_STATUS" },
1839 { 0x019c, "IA32_THERM_STATUS" },
1840 { 0x01a2, "MSR_TEMPERATURE_TARGET" },
1841 { 0x01ad, "MSR_TURBO_RATIO_LIMIT" },
1842 { 0x01ae, "MSR_TURBO_RATIO_LIMIT_CORES" },
1843 { 0x0284, "IA32_MC4_CTL2" },
1844 { 0x0285, "IA32_MC5_CTL2" },
1845 { 0x0286, "IA32_MC6_CTL2" },
1846 { 0x0287, "IA32_MC7_CTL2" },
1847 { 0x0288, "IA32_MC8_CTL2" },
1848 { 0x0289, "IA32_MC9_CTL2" },
1849 { 0x028a, "IA32_MC10_CTL2" },
1850 { 0x028b, "IA32_MC11_CTL2" },
1851 { 0x028c, "IA32_MC12_CTL2" },
1852 { 0x028d, "IA32_MC13_CTL2" },
1853 { 0x028e, "IA32_MC14_CTL2" },
1854 { 0x028f, "IA32_MC15_CTL2" },
1855 { 0x0290, "IA32_MC16_CTL2" },
1856 { 0x0291, "IA32_MC17_CTL2" },
1857 { 0x0292, "IA32_MC18_CTL2" },
1858 { 0x0293, "IA32_MC19_CTL2" },
1859 { 0x0300, "MSR_SGXOWNEREPOCH0" },
1860 { 0x0301, "MSR_SGXOWNEREPOCH1" },
1861 { 0x0410, "IA32_MC4_CTL" },
1862 { 0x0411, "IA32_MC4_STATUS" },
1863 { 0x0412, "IA32_MC4_ADDR" },
1864 { 0x0413, "IA32_MC4_MISC" },
1865 { 0x0414, "IA32_MC5_CTL" },
1866 { 0x0415, "IA32_MC5_STATUS" },
1867 { 0x0416, "IA32_MC5_ADDR" },
1868 { 0x0417, "IA32_MC5_MISC" },
1869 { 0x0418, "IA32_MC6_CTL" },
1870 { 0x0419, "IA32_MC6_STATUS" },
1871 { 0x041a, "IA32_MC6_ADDR" },
1872 { 0x041b, "IA32_MC6_MISC" },
1873 { 0x041c, "IA32_MC7_CTL" },
1874 { 0x041d, "IA32_MC7_STATUS" },
1875 { 0x041e, "IA32_MC7_ADDR" },
1876 { 0x041f, "IA32_MC7_MISC" },
1877 { 0x0420, "IA32_MC8_CTL" },
1878 { 0x0421, "IA32_MC8_STATUS" },
1879 { 0x0422, "IA32_MC8_ADDR" },
1880 { 0x0423, "IA32_MC8_MISC" },
1881 { 0x0424, "IA32_MC9_CTL" },
1882 { 0x0425, "IA32_MC9_STATUS" },
1883 { 0x0426, "IA32_MC9_ADDR" },
1884 { 0x0427, "IA32_MC9_MISC" },
1885 { 0x0428, "IA32_MC10_CTL" },
1886 { 0x0429, "IA32_MC10_STATUS" },
1887 { 0x042a, "IA32_MC10_ADDR" },
1888 { 0x042b, "IA32_MC10_MISC" },
1889 { 0x042c, "IA32_MC11_CTL" },
1890 { 0x042d, "IA32_MC11_STATUS" },
1891 { 0x042e, "IA32_MC11_ADDR" },
1892 { 0x042f, "IA32_MC11_MISC" },
1893 { 0x0430, "IA32_MC12_CTL" },
1894 { 0x0431, "IA32_MC12_STATUS" },
1895 { 0x0432, "IA32_MC12_ADDR" },
1896 { 0x0433, "IA32_MC12_MISC" },
1897 { 0x0434, "IA32_MC13_CTL" },
1898 { 0x0435, "IA32_MC13_STATUS" },
1899 { 0x0436, "IA32_MC13_ADDR" },
1900 { 0x0437, "IA32_MC13_MISC" },
1901 { 0x0438, "IA32_MC14_CTL" },
1902 { 0x0439, "IA32_MC14_STATUS" },
1903 { 0x043a, "IA32_MC14_ADDR" },
1904 { 0x043b, "IA32_MC14_MISC" },
1905 { 0x043c, "IA32_MC15_CTL" },
1906 { 0x043d, "IA32_MC15_STATUS" },
1907 { 0x043e, "IA32_MC15_ADDR" },
1908 { 0x043f, "IA32_MC15_MISC" },
1909 { 0x0440, "IA32_MC16_CTL" },
1910 { 0x0441, "IA32_MC16_STATUS" },
1911 { 0x0442, "IA32_MC16_ADDR" },
1912 { 0x0443, "IA32_MC16_MISC" },
1913 { 0x0444, "IA32_MC17_CTL" },
1914 { 0x0445, "IA32_MC17_STATUS" },
1915 { 0x0446, "IA32_MC17_ADDR" },
1916 { 0x0447, "IA32_MC17_MISC" },
1917 { 0x0448, "IA32_MC18_CTL" },
1918 { 0x0449, "IA32_MC18_STATUS" },
1919 { 0x044a, "IA32_MC18_ADDR" },
1920 { 0x044b, "IA32_MC18_MISC" },
1921 { 0x044c, "IA32_MC19_CTL" },
1922 { 0x044b, "IA32_MC19_STATUS" },
1923 { 0x044e, "IA32_MC19_ADDR" },
1924 { 0x044f, "IA32_MC19_MISC" },
1925 { 0x0606, "MSR_RAPL_POWER_UNIT" },
1926 { 0x0618, "MSR_DRAM_POWER_LIMIT" },
1927 { 0x0619, "MSR_DRAM_ENERGY_STATUS" },
1928 { 0x061b, "MSR_DRAM_PERF_STATUS" },
1929 { 0x061c, "MSR_DRAM_POWER_INFO" },
1930 { 0x0620, "MSR_UNCORE_RATIO_LIMIT" },
1931 { 0x0639, "MSR_PP0_ENERGY_STATUS" },
1932 { 0x0638, "MSR_PP0_POWER_LIMIT" },
1933 { 0x064d, "MSR_PLATFORM_ENERGY_COUNTER" },
1934 { 0x064f, "MSR_CORE_PERF_LIMIT_REASONS" },
1935 { 0x0652, "MSR_PKG_HDC_CONFIG" },
1936 { 0x0655, "MSR_PKG_HDC_SHALLOW_RESIDENCY" },
1937 { 0x0656, "MSR_PKG_HDC_DEEP_RESIDENCY" },
1938 { 0x0658, "MSR_WEIGHTED_CORE_C0" },
1939 { 0x0659, "MSR_ANY_CORE_C0" },
1940 { 0x065a, "MSR_ANY_GFXE_C0" },
1941 { 0x065b, "MSR_CORE_GFXE_OVERLAP_C0" },
1942 { 0x065c, "MSR_PLATFORM_POWER_LIMIT" },
1943 { 0x06b0, "MSR_GRAPHICS_PERF_LIMIT_REASONS" },
1944 { 0x06b1, "MSR_RING_PERF_LIMIT_REASONS" },
1945 { 0x0770, "IA32_PM_ENABLE" },
1946 { 0x0db0, "IA32_PKG_HDC_CTL" },
1947 { 0x0c90, "IA32_L3_QOS_MASK_0" },
1948 { 0x0c91, "IA32_L3_QOS_MASK_1" },
1949 { 0x0c92, "IA32_L3_QOS_MASK_2" },
1950 { 0x0c93, "IA32_L3_QOS_MASK_3" },
1951 { 0x0c94, "IA32_L3_QOS_MASK_4" },
1952 { 0x0c95, "IA32_L3_QOS_MASK_5" },
1953 { 0x0c96, "IA32_L3_QOS_MASK_6" },
1954 { 0x0c97, "IA32_L3_QOS_MASK_7" },
1955 { 0x0c98, "IA32_L3_QOS_MASK_8" },
1956 { 0x0c99, "IA32_L3_QOS_MASK_9" },
1957 { 0x0c9a, "IA32_L3_QOS_MASK_10" },
1958 { 0x0c9b, "IA32_L3_QOS_MASK_11" },
1959 { 0x0c9c, "IA32_L3_QOS_MASK_12" },
1960 { 0x0c9d, "IA32_L3_QOS_MASK_13" },
1961 { 0x0c9e, "IA32_L3_QOS_MASK_14" },
1962 { 0x0c9f, "IA32_L3_QOS_MASK_15" },
1963 };
1964
1965 static const msr_entry_t model565x_per_core_msrs[] = {
1966 { 0x0000, "IA32_P5_MC_ADDR" },
1967 { 0x0001, "IA32_P5_MC_TYPE" },
1968 { 0x0006, "IA32_MONITOR_FILTER_SIZE" },
1969 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
1970 { 0x0017, "IA32_PLATFORM_ID" },
1971 { 0x001b, "IA32_APIC_BASE" },
1972 { 0x0034, "MSR_SMI_COUNT" },
1973 { 0x003a, "IA32_FEATURE_CONTROL" },
1974 { 0x008b, "IA32_BIOS_SIGN_ID" },
1975 { 0x00c1, "IA32_PMC0" },
1976 { 0x00c2, "IA32_PMC1" },
1977 { 0x00c3, "IA32_PMC2" },
1978 { 0x00c4, "IA32_PMC3" },
1979 { 0x00e2, "MSR_PKG_CST_CONFIG_CONTROL" },
1980 { 0x00e4, "MSR_PMG_IO_CAPTURE_BASE" },
1981 { 0x00e7, "IA32_MPERF" },
1982 { 0x00e8, "IA32_APERF" },
1983 { 0x00fe, "IA32_MTRRCAP" },
1984 { 0x013c, "MSR_FEATURE_CONFIG" },
1985 { 0x0174, "IA32_SYSENTER_CS" },
1986 { 0x0175, "IA32_SYSENTER_ESP" },
1987 { 0x0176, "IA32_SYSENTER_EIP" },
1988 { 0x0179, "IA32_MCG_CAP" },
1989 { 0x017a, "IA32_MCG_STATUS" },
1990 { 0x017d, "MSR_SMM_MCA_CAP" },
1991 { 0x0186, "IA32_PERFEVTSEL0" },
1992 { 0x0187, "IA32_PERFEVTSEL1" },
1993 { 0x0188, "IA32_PERFEVTSEL2" },
1994 { 0x0189, "IA32_PERFEVTSEL3" },
1995 { 0x019b, "IA32_THERM_INTERRUPT" },
1996 { 0x0199, "IA32_PERF_CTL" },
1997 { 0x019a, "IA32_CLOCK_MODULATION" },
1998 { 0x01a0, "IA32_MISC_ENABLE" },
1999 { 0x01a4, "IA32_MISC_FEATURE_CONTROL" },
2000 { 0x01a6, "MSR_OFFCORE_RSP_0" },
2001 { 0x01a7, "MSR_OFFCORE_RSP_1" },
2002 { 0x01c8, "MSR_LBR_SELECT" },
2003 { 0x01c9, "MSR_LASTBRANCH_TOS" },
2004 { 0x01d9, "IA32_DEBUGCTL" },
2005 { 0x01dd, "MSR_LER_FROM_LIP" },
2006 { 0x01de, "MSR_LER_TO_LIP" },
2007 { 0x01f2, "IA32_SMRR_PHYSBASE" },
2008 { 0x01f3, "IA32_SMRR_PHYSMASK" },
2009 { 0x01fc, "MSR_POWER_CTL" },
2010 { 0x0200, "IA32_MTRR_PHYSBASE0" },
2011 { 0x0201, "IA32_MTRR_PHYSBASE0" },
2012 { 0x0202, "IA32_MTRR_PHYSBASE1" },
2013 { 0x0203, "IA32_MTRR_PHYSBASE1" },
2014 { 0x0204, "IA32_MTRR_PHYSBASE2" },
2015 { 0x0205, "IA32_MTRR_PHYSBASE2" },
2016 { 0x0206, "IA32_MTRR_PHYSBASE3" },
2017 { 0x0207, "IA32_MTRR_PHYSBASE3" },
2018 { 0x0208, "IA32_MTRR_PHYSBASE4" },
2019 { 0x0209, "IA32_MTRR_PHYSBASE4" },
2020 { 0x020a, "IA32_MTRR_PHYSBASE5" },
2021 { 0x020b, "IA32_MTRR_PHYSBASE5" },
2022 { 0x020c, "IA32_MTRR_PHYSBASE6" },
2023 { 0x020d, "IA32_MTRR_PHYSBASE6" },
2024 { 0x020e, "IA32_MTRR_PHYSBASE7" },
2025 { 0x020f, "IA32_MTRR_PHYSBASE7" },
2026 { 0x0210, "IA32_MTRR_PHYSBASE8" },
2027 { 0x0211, "IA32_MTRR_PHYSBASE8" },
2028 { 0x0212, "IA32_MTRR_PHYSBASE9" },
2029 { 0x0213, "IA32_MTRR_PHYSBASE9" },
2030 { 0x0250, "IA32_MTRR_FIX64K_00000" },
2031 { 0x0258, "IA32_MTRR_FIX16K_80000" },
2032 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
2033 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
2034 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
2035 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
2036 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
2037 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
2038 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
2039 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
2040 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
2041 { 0x0277, "IA32_PAT" },
2042 { 0x0280, "IA32_MC0_CTL2" },
2043 { 0x0281, "IA32_MC1_CTL2" },
2044 { 0x0282, "IA32_MC2_CTL2" },
2045 { 0x0283, "IA32_MC3_CTL2" },
2046 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
2047 { 0x0309, "IA32_FIXED_CTR0" },
2048 { 0x030a, "IA32_FIXED_CTR1" },
2049 { 0x030b, "IA32_FIXED_CTR2" },
2050 { 0x0345, "IA32_PERF_CAPABILITIES" },
2051 { 0x038d, "IA32_FIXED_CTR_CTRL" },
2052 { 0x038e, "IA32_PERF_GLOBAL_STATUS" },
2053 { 0x038f, "IA32_PERF_GLOBAL_CTRL" },
2054 { 0x0390, "IA32_PERF_GLOBAL_STATUS_RESET" },
2055 { 0x0391, "IA32_PERF_GLOBAL_STATUS_SET" },
2056 { 0x0392, "IA32_PERF_GLOBAL_INUSE" },
2057 { 0x03f1, "MSR_PEBS_ENABLE" },
2058 { 0x03f6, "MSR_PEBS_LD_LAT" },
2059 { 0x03f7, "MSR_PEBS_FRONTEND" },
2060 { 0x03fc, "MSR_CORE_C3_RESIDENCY" },
2061 { 0x03fd, "MSR_CORE_C6_RESIDENCY" },
2062 { 0x03fe, "MSR_CORE_C7_RESIDENCY" },
2063 { 0x0400, "IA32_MC0_CTL" },
2064 { 0x0401, "IA32_MC0_STATUS" },
2065 { 0x0402, "IA32_MC0_ADDR" },
2066 { 0x0403, "IA32_MC0_MISC" },
2067 { 0x0404, "IA32_MC1_CTL" },
2068 { 0x0405, "IA32_MC1_STATUS" },
2069 { 0x0406, "IA32_MC1_ADDR" },
2070 { 0x0407, "IA32_MC1_MISC" },
2071 { 0x0408, "IA32_MC2_CTL" },
2072 { 0x0409, "IA32_MC2_STATUS" },
2073 { 0x040a, "IA32_MC2_ADDR" },
2074 { 0x040b, "IA32_MC2_MISC" },
2075 { 0x040c, "IA32_MC3_CTL" },
2076 { 0x040d, "IA32_MC3_STATUS" },
2077 { 0x040e, "IA32_MC3_ADDR" },
2078 { 0x040f, "IA32_MC3_MISC" },
2079 { 0x0480, "IA32_VMX_BASIC" },
2080 { 0x0481, "IA32_VMX_PINBASED_CTLS" },
2081 { 0x0482, "IA32_VMX_PROCBASED_CTLS" },
2082 { 0x0483, "IA32_VMX_EXIT_CTLS" },
2083 { 0x0484, "IA32_VMX_ENTRY_CTLS" },
2084 { 0x0485, "IA32_VMX_MISC" },
2085 { 0x0486, "IA32_VMX_CR0_FIXED0" },
2086 { 0x0487, "IA32_VMX_CR0_FIXED1" },
2087 { 0x0488, "IA32_VMX_CR4_FIXED0" },
2088 { 0x0489, "IA32_VMX_CR4_FIXED1" },
2089 { 0x048a, "IA32_VMX_VMCS_ENUM" },
2090 { 0x048b, "IA32_VMX_PROCBASED_CTLS2" },
2091 { 0x048c, "IA32_VMX_EPT_VPID_ENUM" },
2092 { 0x048d, "IA32_VMX_TRUE_PINBASED_CTLS" },
2093 { 0x048e, "IA32_VMX_TRUE_PROCBASED_CTLS" },
2094 { 0x048f, "IA32_VMX_TRUE_EXIT_CTLS" },
2095 { 0x0490, "IA32_VMX_TRUE_ENTRY_CTLS" },
2096 { 0x04c1, "IA32_A_PMC0" },
2097 { 0x04c2, "IA32_A_PMC1" },
2098 { 0x04c3, "IA32_A_PMC2" },
2099 { 0x04c4, "IA32_A_PMC3" },
2100 { 0x04c5, "IA32_A_PMC4" },
2101 { 0x04c6, "IA32_A_PMC5" },
2102 { 0x04c7, "IA32_A_PMC6" },
2103 { 0x04c8, "IA32_A_PMC7" },
2104 { 0x0500, "IA32_SGX_SVN_STATUS" },
2105 { 0x0560, "IA32_RTIT_OUTPUT_BASE" },
2106 { 0x0561, "IA32_RTIT_OUTPUT_MASK_PTRS" },
2107 { 0x0570, "IA32_RTIT_CTL" },
2108 { 0x0571, "IA32_RTIT_STATUS" },
2109 { 0x0572, "IA32_RTIT_CR3_MATCH" },
2110 { 0x0580, "IA32_RTIT_ADDR0_A" },
2111 { 0x0581, "IA32_RTIT_ADDR0_B" },
2112 { 0x0582, "IA32_RTIT_ADDR1_A" },
2113 { 0x0583, "IA32_RTIT_ADDR1_B" },
2114 { 0x0600, "IA32_DS_AREA" },
2115 { 0x064e, "MSR_PPERF" },
2116 { 0x0653, "MSR_CORE_HDC_RESIDENCY" },
2117 { 0x0690, "MSR_LASTBRANCH_16_FROM_IP" },
2118 { 0x0691, "MSR_LASTBRANCH_17_FROM_IP" },
2119 { 0x0692, "MSR_LASTBRANCH_18_FROM_IP" },
2120 { 0x0693, "MSR_LASTBRANCH_19_FROM_IP" },
2121 { 0x0694, "MSR_LASTBRANCH_20_FROM_IP" },
2122 { 0x0695, "MSR_LASTBRANCH_21_FROM_IP" },
2123 { 0x0696, "MSR_LASTBRANCH_22_FROM_IP" },
2124 { 0x0697, "MSR_LASTBRANCH_23_FROM_IP" },
2125 { 0x0698, "MSR_LASTBRANCH_24_FROM_IP" },
2126 { 0x0699, "MSR_LASTBRANCH_25_FROM_IP" },
2127 { 0x069a, "MSR_LASTBRANCH_26_FROM_IP" },
2128 { 0x069b, "MSR_LASTBRANCH_27_FROM_IP" },
2129 { 0x069c, "MSR_LASTBRANCH_28_FROM_IP" },
2130 { 0x069d, "MSR_LASTBRANCH_29_FROM_IP" },
2131 { 0x069e, "MSR_LASTBRANCH_30_FROM_IP" },
2132 { 0x069f, "MSR_LASTBRANCH_31_FROM_IP" },
2133 { 0x06d0, "MSR_LASTBRANCH_16_TO_IP" },
2134 { 0x06d1, "MSR_LASTBRANCH_17_TO_IP" },
2135 { 0x06d2, "MSR_LASTBRANCH_18_TO_IP" },
2136 { 0x06d3, "MSR_LASTBRANCH_19_TO_IP" },
2137 { 0x06d4, "MSR_LASTBRANCH_20_TO_IP" },
2138 { 0x06d5, "MSR_LASTBRANCH_21_TO_IP" },
2139 { 0x06d6, "MSR_LASTBRANCH_22_TO_IP" },
2140 { 0x06d7, "MSR_LASTBRANCH_23_TO_IP" },
2141 { 0x06d8, "MSR_LASTBRANCH_24_TO_IP" },
2142 { 0x06d9, "MSR_LASTBRANCH_25_TO_IP" },
2143 { 0x06da, "MSR_LASTBRANCH_26_TO_IP" },
2144 { 0x06db, "MSR_LASTBRANCH_27_TO_IP" },
2145 { 0x06dc, "MSR_LASTBRANCH_28_TO_IP" },
2146 { 0x06dd, "MSR_LASTBRANCH_29_TO_IP" },
2147 { 0x06de, "MSR_LASTBRANCH_30_TO_IP" },
2148 { 0x06df, "MSR_LASTBRANCH_31_TO_IP" },
2149 { 0x06e0, "IA32_TSC_DEADLINE" },
2150 { 0x0771, "IA32_HWP_CAPABILITIES" },
2151 { 0x0773, "IA32_HWP_INTERRUPT" },
2152 { 0x0774, "IA32_HWP_REQUEST" },
2153 { 0x0777, "IA32_HWP_STATUS" },
2154 { 0x0c8d, "IA32_QM_EVTSEL" },
2155 { 0x0c8f, "IA32_PQR_ASSOC" },
2156 { 0x0d90, "IA32_BNDCFGS" },
2157 { 0x0da0, "IA32_XSS" },
2158 { 0x0db1, "IA32_PM_CTL1" },
2159 { 0x0db2, "IA32_THREAD_STALL" },
2160 { 0x0dc0, "MSR_LBR_INFO_0" },
2161 { 0x0dc1, "MSR_LBR_INFO_1" },
2162 { 0x0dc2, "MSR_LBR_INFO_2" },
2163 { 0x0dc3, "MSR_LBR_INFO_3" },
2164 { 0x0dc4, "MSR_LBR_INFO_4" },
2165 { 0x0dc5, "MSR_LBR_INFO_5" },
2166 { 0x0dc6, "MSR_LBR_INFO_6" },
2167 { 0x0dc7, "MSR_LBR_INFO_7" },
2168 { 0x0dc8, "MSR_LBR_INFO_8" },
2169 { 0x0dc9, "MSR_LBR_INFO_9" },
2170 { 0x0dca, "MSR_LBR_INFO_10" },
2171 { 0x0dcb, "MSR_LBR_INFO_11" },
2172 { 0x0dcc, "MSR_LBR_INFO_12" },
2173 { 0x0dcd, "MSR_LBR_INFO_13" },
2174 { 0x0dce, "MSR_LBR_INFO_14" },
2175 { 0x0dcf, "MSR_LBR_INFO_15" },
2176 { 0x0dd0, "MSR_LBR_INFO_16" },
2177 { 0x0dd1, "MSR_LBR_INFO_17" },
2178 { 0x0dd2, "MSR_LBR_INFO_18" },
2179 { 0x0dd3, "MSR_LBR_INFO_19" },
2180 { 0x0dd4, "MSR_LBR_INFO_20" },
2181 { 0x0dd5, "MSR_LBR_INFO_21" },
2182 { 0x0dd6, "MSR_LBR_INFO_22" },
2183 { 0x0dd7, "MSR_LBR_INFO_23" },
2184 { 0x0dd8, "MSR_LBR_INFO_24" },
2185 { 0x0dd9, "MSR_LBR_INFO_25" },
2186 { 0x0ddA, "MSR_LBR_INFO_26" },
2187 { 0x0ddB, "MSR_LBR_INFO_27" },
2188 { 0x0ddc, "MSR_LBR_INFO_28" },
2189 { 0x0ddd, "MSR_LBR_INFO_29" },
2190 { 0x0dde, "MSR_LBR_INFO_30" },
2191 { 0x0ddf, "MSR_LBR_INFO_31" },
2192 };
2193
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]2194 typedef struct {
2195 unsigned int model;
2196 const msr_entry_t *global_msrs;
2197 unsigned int num_global_msrs;
2198 const msr_entry_t *per_core_msrs;
2199 unsigned int num_per_core_msrs;
2200 } cpu_t;
2201
2202 cpu_t cpulist[] = {
Tobias Diedrich3645e612010-11-27 14:44:19 +0000[diff] [blame]2203 { 0x00670, model67x_global_msrs, ARRAY_SIZE(model67x_global_msrs), NULL, 0 },
Stefan Reinauer04844812010-02-22 11:26:06 +0000[diff] [blame]2204 { 0x006b0, model6bx_global_msrs, ARRAY_SIZE(model6bx_global_msrs), NULL, 0 },
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]2205 { 0x006e0, model6ex_global_msrs, ARRAY_SIZE(model6ex_global_msrs), model6ex_per_core_msrs, ARRAY_SIZE(model6ex_per_core_msrs) },
2206 { 0x006f0, model6fx_global_msrs, ARRAY_SIZE(model6fx_global_msrs), model6fx_per_core_msrs, ARRAY_SIZE(model6fx_per_core_msrs) },
Idwer Vollering312fc962010-12-17 22:34:58 +0000[diff] [blame]2207 { 0x00f20, modelf2x_global_msrs, ARRAY_SIZE(modelf2x_global_msrs), modelf2x_per_core_msrs, ARRAY_SIZE(modelf2x_per_core_msrs) },
Pat Erleyca3548e2010-04-21 06:23:19 +0000[diff] [blame]2208 { 0x00f40, modelf4x_global_msrs, ARRAY_SIZE(modelf4x_global_msrs), modelf4x_per_core_msrs, ARRAY_SIZE(modelf4x_per_core_msrs) },
Elyes HAOUASdfe8d642018-01-31 21:29:00 +0100[diff] [blame]2209 { 0x00f60, modelf6x_global_msrs, ARRAY_SIZE(modelf6x_global_msrs), modelf6x_per_core_msrs, ARRAY_SIZE(modelf6x_per_core_msrs) },
Olivier Langlois70f39872013-01-25 00:49:46 -0500[diff] [blame]2210 { 0x106c0, model6_atom_global_msrs, ARRAY_SIZE(model6_atom_global_msrs), model6_atom_per_core_msrs, ARRAY_SIZE(model6_atom_per_core_msrs) },
Vladimir Serbinenkoe4e8e092013-03-31 13:51:37 +0200[diff] [blame]2211 { 0x20650, model20650_global_msrs, ARRAY_SIZE(model20650_global_msrs), model20650_per_core_msrs, ARRAY_SIZE(model20650_per_core_msrs) },
Christian Walter9a8c5e72019-05-06 17:50:57 +0200[diff] [blame]2212 { 0x906e0, model96ex_global_msrs, ARRAY_SIZE(model96ex_global_msrs), model96ex_per_core_msrs, ARRAY_SIZE(model96ex_per_core_msrs) },
Maxim Polyakov9af10bf2019-10-08 17:33:59 +0300[diff] [blame]2213 { 0x50650, model565x_global_msrs, ARRAY_SIZE(model565x_global_msrs), model565x_per_core_msrs, ARRAY_SIZE(model565x_per_core_msrs) },
Martin Roth51dde6f2014-12-07 22:11:54 -0700[diff] [blame]2214
2215 { CPUID_BAYTRAIL, silvermont_global_msrs, ARRAY_SIZE(silvermont_global_msrs), silvermont_per_core_msrs, ARRAY_SIZE(silvermont_per_core_msrs) }, /* Baytrail */
2216
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]2217 };
2218
2219 cpu_t *cpu = NULL;
2220
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]2221 /* Get CPU family and model, not the stepping
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]2222 * (TODO: extended family/model)
2223 */
Stefan Reinauer74cd56982010-06-01 10:04:28 +0000[diff] [blame]2224 id = cpuid(1) & 0xfffff0;
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]2225 for (i = 0; i < ARRAY_SIZE(cpulist); i++) {
2226 if(cpulist[i].model == id) {
2227 cpu = &cpulist[i];
2228 break;
2229 }
2230 }
2231
2232 if (!cpu) {
2233 printf("Error: Dumping MSRs on this CPU (0x%06x) is not (yet) supported.\n", id);
2234 return -1;
2235 }
2236
Stefan Reinauerf7f2f252009-09-01 09:52:14 +0000[diff] [blame]2237#ifndef __DARWIN__
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]2238 fd_msr = open("/dev/cpu/0/msr", O_RDWR);
2239 if (fd_msr < 0) {
2240 perror("Error while opening /dev/cpu/0/msr");
2241 printf("Did you run 'modprobe msr'?\n");
2242 return -1;
2243 }
Stefan Reinauer1162f252008-12-04 15:18:20 +0000[diff] [blame]2244#endif
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]2245
2246 printf("\n===================== SHARED MSRs (All Cores) =====================\n");
2247
2248 for (i = 0; i < cpu->num_global_msrs; i++) {
2249 msr = rdmsr(cpu->global_msrs[i].number);
2250 printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n",
2251 cpu->global_msrs[i].number, msr.hi, msr.lo,
2252 cpu->global_msrs[i].name);
2253 }
2254
2255 close(fd_msr);
2256
Maxim Polyakov9af10bf2019-10-08 17:33:59 +0300[diff] [blame]2257 for (core = 0; core < core_num; core++) {
Stefan Reinauerf7f2f252009-09-01 09:52:14 +0000[diff] [blame]2258#ifndef __DARWIN__
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]2259 char msrfilename[64];
2260 memset(msrfilename, 0, 64);
Paul Menzel5f3754e2013-04-05 00:12:21 +0200[diff] [blame]2261 sprintf(msrfilename, "/dev/cpu/%u/msr", core);
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]2262
2263 fd_msr = open(msrfilename, O_RDWR);
2264
2265 /* If the file is not there, we're probably through. No error,
2266 * since we successfully opened /dev/cpu/0/msr before.
2267 */
2268 if (fd_msr < 0)
2269 break;
Stefan Reinauer1162f252008-12-04 15:18:20 +0000[diff] [blame]2270#endif
Stefan Reinauer04844812010-02-22 11:26:06 +0000[diff] [blame]2271 if (cpu->num_per_core_msrs)
Paul Menzel5f3754e2013-04-05 00:12:21 +0200[diff] [blame]2272 printf("\n====================== UNIQUE MSRs (core %u) ======================\n", core);
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]2273
2274 for (i = 0; i < cpu->num_per_core_msrs; i++) {
2275 msr = rdmsr(cpu->per_core_msrs[i].number);
2276 printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n",
2277 cpu->per_core_msrs[i].number, msr.hi, msr.lo,
2278 cpu->per_core_msrs[i].name);
2279 }
Stefan Reinauerf7f2f252009-09-01 09:52:14 +0000[diff] [blame]2280#ifndef __DARWIN__
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]2281 close(fd_msr);
Stefan Reinauer1162f252008-12-04 15:18:20 +0000[diff] [blame]2282#endif
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]2283 }
2284
Stefan Reinauerf7f2f252009-09-01 09:52:14 +0000[diff] [blame]2285#ifndef __DARWIN__
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]2286 if (msr_readerror)
2287 printf("\n(*) Some MSRs could not be read. The marked values are unreliable.\n");
Stefan Reinauer1162f252008-12-04 15:18:20 +0000[diff] [blame]2288#endif
Stefan Reinauer23190272008-08-20 13:41:24 +0000[diff] [blame]2289 return 0;
2290}