Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 2 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 3 | #include <commonlib/helpers.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 4 | #include <console/console.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 5 | #include <device/pci_ops.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 6 | #include <acpi/acpi.h> |
| 7 | #include <acpi/acpi_ivrs.h> |
Michał Żygowski | 208318c | 2020-03-20 15:54:27 +0100 | [diff] [blame] | 8 | #include <arch/ioapic.h> |
Felix Held | 61dd31c | 2023-06-05 19:38:36 +0200 | [diff] [blame] | 9 | #include <arch/vga.h> |
Elyes HAOUAS | 146d0c2 | 2020-07-22 11:47:08 +0200 | [diff] [blame] | 10 | #include <types.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 11 | #include <device/device.h> |
| 12 | #include <device/pci.h> |
| 13 | #include <device/pci_ids.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 14 | #include <string.h> |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 15 | #include <stdlib.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 16 | #include <lib.h> |
Michał Kopeć | dc35d2a | 2021-11-30 17:40:52 +0100 | [diff] [blame] | 17 | #include <cpu/x86/mp.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 18 | #include <Porting.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 19 | #include <Topology.h> |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 20 | #include <cpu/amd/msr.h> |
| 21 | #include <cpu/amd/mtrr.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 22 | #include <acpi/acpigen.h> |
Angel Pons | ec5cf15 | 2020-11-10 20:42:07 +0100 | [diff] [blame] | 23 | #include <northbridge/amd/nb_common.h> |
Kyösti Mälkki | ed8d277 | 2017-07-15 17:12:44 +0300 | [diff] [blame] | 24 | #include <northbridge/amd/agesa/agesa_helper.h> |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 25 | #include <southbridge/amd/pi/hudson/pci_devs.h> |
Arthur Heymans | 44807ac | 2022-09-13 12:43:37 +0200 | [diff] [blame] | 26 | #include <amdblocks/cpu.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 27 | |
Michał Żygowski | 6ca5b47 | 2019-09-10 15:10:22 +0200 | [diff] [blame] | 28 | #define PCIE_CAP_AER BIT(5) |
| 29 | #define PCIE_CAP_ACS BIT(6) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 30 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 31 | static struct device *get_node_pci(u32 nodeid, u32 fn) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 32 | { |
Kyösti Mälkki | bbd2377 | 2019-01-10 05:41:23 +0200 | [diff] [blame] | 33 | return pcidev_on_root(DEV_CDB + nodeid, fn); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 34 | } |
| 35 | |
Felix Held | 3eaa850 | 2023-12-16 01:37:34 +0100 | [diff] [blame] | 36 | static int get_dram_base_limit(resource_t *basek, resource_t *limitk) |
Michał Żygowski | 88a0ce6 | 2021-05-05 09:52:59 +0200 | [diff] [blame] | 37 | { |
| 38 | u32 temp; |
| 39 | |
Felix Held | 3eaa850 | 2023-12-16 01:37:34 +0100 | [diff] [blame] | 40 | temp = pci_read_config32(get_node_pci(0, 1), 0x40); //[39:24] at [31:16] |
Michał Żygowski | 88a0ce6 | 2021-05-05 09:52:59 +0200 | [diff] [blame] | 41 | if (!(temp & 1)) |
| 42 | return 0; // this memory range is not enabled |
| 43 | /* |
| 44 | * BKDG: {DramBase[39:24], 00_0000h} <= address[39:0] so shift left by 8 bits |
| 45 | * for physical address and the convert to KiB by shifting 10 bits left |
| 46 | */ |
| 47 | *basek = ((temp & 0xffff0000)) >> (10 - 8); |
| 48 | /* |
| 49 | * BKDG address[39:0] <= {DramLimit[39:24], FF_FFFFh} converted as above but |
| 50 | * ORed with 0xffff to get real limit before shifting. |
| 51 | */ |
Felix Held | 3eaa850 | 2023-12-16 01:37:34 +0100 | [diff] [blame] | 52 | temp = pci_read_config32(get_node_pci(0, 1), 0x44); //[39:24] at [31:16] |
Michał Żygowski | 88a0ce6 | 2021-05-05 09:52:59 +0200 | [diff] [blame] | 53 | *limitk = ((temp & 0xffff0000) | 0xffff) >> (10 - 8); |
| 54 | *limitk += 1; // round up last byte |
| 55 | |
| 56 | return 1; |
| 57 | } |
| 58 | |
Michał Żygowski | 58d6f96 | 2021-05-05 10:52:08 +0200 | [diff] [blame] | 59 | static void add_fixed_resources(struct device *dev, int index) |
| 60 | { |
| 61 | /* Reserve everything between A segment and 1MB: |
| 62 | * |
| 63 | * 0xa0000 - 0xbffff: legacy VGA |
| 64 | * 0xc0000 - 0xfffff: option ROMs and SeaBIOS (if used) |
| 65 | */ |
Felix Held | 61dd31c | 2023-06-05 19:38:36 +0200 | [diff] [blame] | 66 | mmio_resource_kb(dev, index++, VGA_MMIO_BASE >> 10, VGA_MMIO_SIZE >> 10); |
Kyösti Mälkki | 27d6299 | 2022-05-24 20:25:58 +0300 | [diff] [blame] | 67 | reserved_ram_resource_kb(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); |
Michał Żygowski | 58d6f96 | 2021-05-05 10:52:08 +0200 | [diff] [blame] | 68 | |
Michał Żygowski | 58d6f96 | 2021-05-05 10:52:08 +0200 | [diff] [blame] | 69 | /* Check if CC6 save area is enabled (bit 18 CC6SaveEn) */ |
Felix Held | 606e563 | 2023-11-16 18:34:33 +0100 | [diff] [blame] | 70 | if (pci_read_config32(get_node_pci(0, 2), 0x118) & (1 << 18)) { |
Michał Żygowski | 58d6f96 | 2021-05-05 10:52:08 +0200 | [diff] [blame] | 71 | /* Add CC6 DRAM UC resource residing at DRAM Limit of size 16MB as per BKDG */ |
| 72 | resource_t basek, limitk; |
Felix Held | 3eaa850 | 2023-12-16 01:37:34 +0100 | [diff] [blame] | 73 | if (!get_dram_base_limit(&basek, &limitk)) |
Michał Żygowski | 58d6f96 | 2021-05-05 10:52:08 +0200 | [diff] [blame] | 74 | return; |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 75 | mmio_resource_kb(dev, index++, limitk, 16 * 1024); |
Michał Żygowski | 58d6f96 | 2021-05-05 10:52:08 +0200 | [diff] [blame] | 76 | } |
| 77 | } |
| 78 | |
Michał Żygowski | fb198c6 | 2021-05-09 13:54:09 +0200 | [diff] [blame] | 79 | static void nb_read_resources(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 80 | { |
Kyösti Mälkki | 5d49038 | 2015-05-27 07:58:22 +0300 | [diff] [blame] | 81 | /* |
| 82 | * This MMCONF resource must be reserved in the PCI domain. |
| 83 | * It is not honored by the coreboot resource allocator if it is in |
| 84 | * the CPU_CLUSTER. |
| 85 | */ |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 86 | mmconf_resource(dev, MMIO_CONF_BASE); |
Michał Żygowski | 208318c | 2020-03-20 15:54:27 +0100 | [diff] [blame] | 87 | |
| 88 | /* NB IOAPIC2 resource */ |
Felix Held | 8f0075c | 2023-08-09 19:28:39 +0200 | [diff] [blame] | 89 | mmio_range(dev, IO_APIC2_ADDR, IO_APIC2_ADDR, 0x1000); |
Michał Żygowski | 58d6f96 | 2021-05-05 10:52:08 +0200 | [diff] [blame] | 90 | |
| 91 | add_fixed_resources(dev, 0); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 92 | } |
| 93 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 94 | static void northbridge_init(struct device *dev) |
| 95 | { |
Kyösti Mälkki | d1534e4 | 2023-04-09 10:01:58 +0300 | [diff] [blame] | 96 | register_new_ioapic((u8 *)IO_APIC2_ADDR); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 97 | } |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 98 | |
Vladimir Serbinenko | 807127f | 2014-11-09 13:36:18 +0100 | [diff] [blame] | 99 | static unsigned long acpi_fill_hest(acpi_hest_t *hest) |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 100 | { |
| 101 | void *addr, *current; |
| 102 | |
| 103 | /* Skip the HEST header. */ |
| 104 | current = (void *)(hest + 1); |
| 105 | |
| 106 | addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); |
| 107 | if (addr != NULL) |
| 108 | current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); |
| 109 | |
| 110 | addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); |
| 111 | if (addr != NULL) |
| 112 | current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); |
| 113 | |
| 114 | return (unsigned long)current; |
| 115 | } |
| 116 | |
Arthur Heymans | f9ee87f | 2023-06-07 15:29:02 +0200 | [diff] [blame] | 117 | static unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 118 | { |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 119 | /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ |
| 120 | current = ALIGN_UP(current, 8); |
| 121 | ivrs_ivhd_special_t *ivhd_ioapic = (ivrs_ivhd_special_t *)current; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 122 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 123 | ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; |
| 124 | ivhd_ioapic->reserved = 0x0000; |
| 125 | ivhd_ioapic->dte_setting = IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS | |
| 126 | IVHD_DTE_SYS_MGT_NO_TRANS | IVHD_DTE_NMI_PASS | |
| 127 | IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS; |
Kyösti Mälkki | d1534e4 | 2023-04-09 10:01:58 +0300 | [diff] [blame] | 128 | ivhd_ioapic->handle = get_ioapic_id(VIO_APIC_VADDR); |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 129 | ivhd_ioapic->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); |
| 130 | ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; |
| 131 | current += sizeof(ivrs_ivhd_special_t); |
| 132 | |
| 133 | ivhd_ioapic = (ivrs_ivhd_special_t *)current; |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 134 | ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; |
| 135 | ivhd_ioapic->reserved = 0x0000; |
| 136 | ivhd_ioapic->dte_setting = 0x00; |
Kyösti Mälkki | d1534e4 | 2023-04-09 10:01:58 +0300 | [diff] [blame] | 137 | ivhd_ioapic->handle = get_ioapic_id((u8 *)IO_APIC2_ADDR); |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 138 | ivhd_ioapic->source_dev_id = PCI_DEVFN(0, 1); |
| 139 | ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; |
| 140 | current += sizeof(ivrs_ivhd_special_t); |
| 141 | |
| 142 | return current; |
| 143 | } |
| 144 | |
| 145 | static unsigned long ivhd_describe_hpet(unsigned long current) |
| 146 | { |
| 147 | /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ |
| 148 | current = ALIGN_UP(current, 8); |
| 149 | ivrs_ivhd_special_t *ivhd_hpet = (ivrs_ivhd_special_t *)current; |
| 150 | |
| 151 | ivhd_hpet->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; |
| 152 | ivhd_hpet->reserved = 0x0000; |
| 153 | ivhd_hpet->dte_setting = 0x00; |
| 154 | ivhd_hpet->handle = 0x00; |
| 155 | ivhd_hpet->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); |
| 156 | ivhd_hpet->variety = IVHD_SPECIAL_DEV_HPET; |
| 157 | current += sizeof(ivrs_ivhd_special_t); |
| 158 | |
| 159 | return current; |
| 160 | } |
| 161 | |
| 162 | static unsigned long ivhd_dev_range(unsigned long current, uint16_t start_devid, |
| 163 | uint16_t end_devid, uint8_t setting) |
| 164 | { |
| 165 | /* 4-byte IVHD structures must be aligned to the 4-byte boundary. */ |
| 166 | current = ALIGN_UP(current, 4); |
| 167 | ivrs_ivhd_generic_t *ivhd_range = (ivrs_ivhd_generic_t *)current; |
| 168 | |
| 169 | /* Create the start range IVHD entry */ |
| 170 | ivhd_range->type = IVHD_DEV_4_BYTE_START_RANGE; |
| 171 | ivhd_range->dev_id = start_devid; |
| 172 | ivhd_range->dte_setting = setting; |
| 173 | current += sizeof(ivrs_ivhd_generic_t); |
| 174 | |
| 175 | /* Create the end range IVHD entry */ |
| 176 | ivhd_range = (ivrs_ivhd_generic_t *)current; |
| 177 | ivhd_range->type = IVHD_DEV_4_BYTE_END_RANGE; |
| 178 | ivhd_range->dev_id = end_devid; |
| 179 | ivhd_range->dte_setting = setting; |
| 180 | current += sizeof(ivrs_ivhd_generic_t); |
| 181 | |
| 182 | return current; |
| 183 | } |
| 184 | |
| 185 | static unsigned long add_ivhd_dev_entry(struct device *parent, struct device *dev, |
| 186 | unsigned long *current, uint8_t type, uint8_t data) |
| 187 | { |
| 188 | if (type == IVHD_DEV_4_BYTE_SELECT) { |
| 189 | /* 4-byte IVHD structures must be aligned to the 4-byte boundary. */ |
| 190 | *current = ALIGN_UP(*current, 4); |
| 191 | ivrs_ivhd_generic_t *ivhd_entry = (ivrs_ivhd_generic_t *)*current; |
| 192 | |
| 193 | ivhd_entry->type = type; |
| 194 | ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); |
| 195 | ivhd_entry->dte_setting = data; |
| 196 | *current += sizeof(ivrs_ivhd_generic_t); |
| 197 | } else if (type == IVHD_DEV_8_BYTE_ALIAS_SELECT) { |
| 198 | /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ |
| 199 | *current = ALIGN_UP(*current, 8); |
| 200 | ivrs_ivhd_alias_t *ivhd_entry = (ivrs_ivhd_alias_t *)*current; |
| 201 | |
| 202 | ivhd_entry->type = type; |
| 203 | ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); |
| 204 | ivhd_entry->dte_setting = data; |
| 205 | ivhd_entry->reserved1 = 0; |
| 206 | ivhd_entry->reserved2 = 0; |
| 207 | ivhd_entry->source_dev_id = parent->path.pci.devfn | |
| 208 | (parent->bus->secondary << 8); |
| 209 | *current += sizeof(ivrs_ivhd_alias_t); |
| 210 | } |
| 211 | |
| 212 | return *current; |
| 213 | } |
| 214 | |
| 215 | static void ivrs_add_device_or_bridge(struct device *parent, struct device *dev, |
| 216 | unsigned long *current, uint16_t *ivhd_length) |
| 217 | { |
| 218 | unsigned int header_type, is_pcie; |
| 219 | unsigned long current_backup; |
| 220 | |
| 221 | header_type = dev->hdr_type & 0x7f; |
| 222 | is_pcie = pci_find_capability(dev, PCI_CAP_ID_PCIE); |
| 223 | |
| 224 | if (((header_type == PCI_HEADER_TYPE_NORMAL) || |
| 225 | (header_type == PCI_HEADER_TYPE_BRIDGE)) && is_pcie) { |
| 226 | /* Device or Bridge is PCIe */ |
| 227 | current_backup = *current; |
| 228 | add_ivhd_dev_entry(parent, dev, current, IVHD_DEV_4_BYTE_SELECT, 0x0); |
| 229 | *ivhd_length += (*current - current_backup); |
| 230 | } else if ((header_type == PCI_HEADER_TYPE_NORMAL) && !is_pcie) { |
| 231 | /* Device is legacy PCI or PCI-X */ |
| 232 | current_backup = *current; |
| 233 | add_ivhd_dev_entry(parent, dev, current, IVHD_DEV_8_BYTE_ALIAS_SELECT, 0x0); |
| 234 | *ivhd_length += (*current - current_backup); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 235 | } |
| 236 | } |
| 237 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 238 | static void add_ivhd_device_entries(struct device *parent, struct device *dev, |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 239 | unsigned int depth, int linknum, int8_t *root_level, |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 240 | unsigned long *current, uint16_t *ivhd_length) |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 241 | { |
| 242 | struct device *sibling; |
| 243 | struct bus *link; |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 244 | |
| 245 | if (!root_level) { |
| 246 | root_level = malloc(sizeof(int8_t)); |
| 247 | *root_level = -1; |
| 248 | } |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 249 | |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 250 | if (dev->path.type == DEVICE_PATH_PCI) { |
| 251 | |
| 252 | if ((dev->bus->secondary == 0x0) && |
| 253 | (dev->path.pci.devfn == 0x0)) |
| 254 | *root_level = depth; |
| 255 | |
| 256 | if ((*root_level != -1) && (dev->enabled)) { |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 257 | if (depth != *root_level) |
| 258 | ivrs_add_device_or_bridge(parent, dev, current, ivhd_length); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 259 | } |
| 260 | } |
| 261 | |
| 262 | for (link = dev->link_list; link; link = link->next) |
| 263 | for (sibling = link->children; sibling; sibling = |
| 264 | sibling->sibling) |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 265 | add_ivhd_device_entries(dev, sibling, depth + 1, depth, root_level, |
| 266 | current, ivhd_length); |
| 267 | |
| 268 | free(root_level); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 269 | } |
| 270 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 271 | #define IOMMU_MMIO32(x) (*((volatile uint32_t *)(x))) |
| 272 | #define EFR_SUPPORT BIT(27) |
| 273 | |
| 274 | static unsigned long acpi_fill_ivrs11(unsigned long current, acpi_ivrs_t *ivrs_agesa) |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 275 | { |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 276 | acpi_ivrs_ivhd11_t *ivhd_11; |
| 277 | unsigned long current_backup; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 278 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 279 | /* |
| 280 | * These devices should be already found by previous function. |
| 281 | * Do not perform NULL checks. |
| 282 | */ |
| 283 | struct device *nb_dev = pcidev_on_root(0, 0); |
| 284 | struct device *iommu_dev = pcidev_on_root(0, 2); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 285 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 286 | /* |
| 287 | * In order to utilize all features, firmware should expose type 11h |
| 288 | * IVHD which supersedes the type 10h. |
| 289 | */ |
| 290 | memset((void *)current, 0, sizeof(acpi_ivrs_ivhd11_t)); |
| 291 | ivhd_11 = (acpi_ivrs_ivhd11_t *)current; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 292 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 293 | /* Enable EFR */ |
| 294 | ivhd_11->type = IVHD_BLOCK_TYPE_FULL__FIXED; |
| 295 | /* For type 11h bits 6 and 7 are reserved */ |
| 296 | ivhd_11->flags = ivrs_agesa->ivhd.flags & 0x3f; |
| 297 | ivhd_11->length = sizeof(struct acpi_ivrs_ivhd_11); |
| 298 | /* BDF <bus>:00.2 */ |
| 299 | ivhd_11->device_id = 0x02 | (nb_dev->bus->secondary << 8); |
| 300 | /* PCI Capability block 0x40 (type 0xf, "Secure device") */ |
| 301 | ivhd_11->capability_offset = 0x40; |
| 302 | ivhd_11->iommu_base_low = ivrs_agesa->ivhd.iommu_base_low; |
| 303 | ivhd_11->iommu_base_high = ivrs_agesa->ivhd.iommu_base_high; |
| 304 | ivhd_11->pci_segment_group = 0x0000; |
| 305 | ivhd_11->iommu_info = ivrs_agesa->ivhd.iommu_info; |
| 306 | ivhd_11->iommu_attributes.perf_counters = |
| 307 | (IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x4000) >> 7) & 0xf; |
| 308 | ivhd_11->iommu_attributes.perf_counter_banks = |
| 309 | (IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x4000) >> 12) & 0x3f; |
| 310 | ivhd_11->iommu_attributes.msi_num_ppr = |
| 311 | (pci_read_config32(iommu_dev, ivhd_11->capability_offset + 0x10) >> 27) & 0x1f; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 312 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 313 | if (pci_read_config32(iommu_dev, ivhd_11->capability_offset) & EFR_SUPPORT) { |
| 314 | ivhd_11->efr_reg_image_low = IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x30); |
| 315 | ivhd_11->efr_reg_image_high = IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x34); |
| 316 | } |
| 317 | |
| 318 | current += sizeof(acpi_ivrs_ivhd11_t); |
| 319 | |
| 320 | /* Now repeat all the device entries from type 10h */ |
| 321 | current_backup = current; |
| 322 | current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0); |
| 323 | ivhd_11->length += (current - current_backup); |
| 324 | add_ivhd_device_entries(NULL, all_devices, 0, -1, NULL, ¤t, &ivhd_11->length); |
| 325 | |
| 326 | /* Describe HPET */ |
| 327 | current_backup = current; |
| 328 | current = ivhd_describe_hpet(current); |
| 329 | ivhd_11->length += (current - current_backup); |
| 330 | |
| 331 | /* Describe IOAPICs */ |
| 332 | current_backup = current; |
| 333 | current = acpi_fill_ivrs_ioapic(ivrs_agesa, current); |
| 334 | ivhd_11->length += (current - current_backup); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 335 | |
| 336 | return current; |
| 337 | } |
| 338 | |
| 339 | static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current) |
| 340 | { |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 341 | acpi_ivrs_t *ivrs_agesa; |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 342 | unsigned long current_backup; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 343 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 344 | struct device *nb_dev = pcidev_on_root(0, 0); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 345 | if (!nb_dev) { |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 346 | printk(BIOS_WARNING, "%s: G-series northbridge device not present!\n", __func__); |
| 347 | printk(BIOS_WARNING, "%s: IVRS table not generated...\n", __func__); |
| 348 | |
| 349 | return (unsigned long)ivrs; |
| 350 | } |
| 351 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 352 | struct device *iommu_dev = pcidev_on_root(0, 2); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 353 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 354 | if (!iommu_dev) { |
| 355 | printk(BIOS_WARNING, "%s: IOMMU device not found\n", __func__); |
| 356 | |
| 357 | return (unsigned long)ivrs; |
| 358 | } |
| 359 | |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 360 | ivrs_agesa = agesawrapper_getlateinitptr(PICK_IVRS); |
| 361 | if (ivrs_agesa != NULL) { |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 362 | ivrs->iv_info = ivrs_agesa->iv_info; |
| 363 | ivrs->ivhd.type = IVHD_BLOCK_TYPE_LEGACY__FIXED; |
| 364 | ivrs->ivhd.flags = ivrs_agesa->ivhd.flags; |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 365 | ivrs->ivhd.length = sizeof(struct acpi_ivrs_ivhd); |
| 366 | /* BDF <bus>:00.2 */ |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 367 | ivrs->ivhd.device_id = 0x02 | (nb_dev->bus->secondary << 8); |
| 368 | /* PCI Capability block 0x40 (type 0xf, "Secure device") */ |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 369 | ivrs->ivhd.capability_offset = 0x40; |
| 370 | ivrs->ivhd.iommu_base_low = ivrs_agesa->ivhd.iommu_base_low; |
| 371 | ivrs->ivhd.iommu_base_high = ivrs_agesa->ivhd.iommu_base_high; |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 372 | ivrs->ivhd.pci_segment_group = 0x0000; |
| 373 | ivrs->ivhd.iommu_info = ivrs_agesa->ivhd.iommu_info; |
| 374 | ivrs->ivhd.iommu_feature_info = ivrs_agesa->ivhd.iommu_feature_info; |
| 375 | /* Enable EFR if supported */ |
| 376 | if (pci_read_config32(iommu_dev, ivrs->ivhd.capability_offset) & EFR_SUPPORT) |
| 377 | ivrs->iv_info |= IVINFO_EFR_SUPPORTED; |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 378 | } else { |
| 379 | printk(BIOS_WARNING, "%s: AGESA returned NULL IVRS\n", __func__); |
| 380 | |
| 381 | return (unsigned long)ivrs; |
| 382 | } |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 383 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 384 | /* |
| 385 | * Add all possible PCI devices on bus 0 that can generate transactions |
| 386 | * processed by IOMMU. Start with device 00:01.0 since IOMMU does not |
| 387 | * translate transactions generated by itself. |
| 388 | */ |
| 389 | current_backup = current; |
| 390 | current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0); |
| 391 | ivrs->ivhd.length += (current - current_backup); |
| 392 | add_ivhd_device_entries(NULL, all_devices, 0, -1, NULL, ¤t, &ivrs->ivhd.length); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 393 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 394 | /* Describe HPET */ |
| 395 | current_backup = current; |
| 396 | current = ivhd_describe_hpet(current); |
| 397 | ivrs->ivhd.length += (current - current_backup); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 398 | |
| 399 | /* Describe IOAPICs */ |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 400 | current_backup = current; |
| 401 | current = acpi_fill_ivrs_ioapic(ivrs_agesa, current); |
| 402 | ivrs->ivhd.length += (current - current_backup); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 403 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 404 | /* If EFR is not supported, IVHD type 11h is reserved */ |
| 405 | if (!(ivrs->iv_info & IVINFO_EFR_SUPPORTED)) |
| 406 | return current; |
| 407 | |
| 408 | return acpi_fill_ivrs11(current, ivrs_agesa); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 409 | } |
| 410 | |
Furquan Shaikh | 7536a39 | 2020-04-24 21:59:21 -0700 | [diff] [blame] | 411 | static void northbridge_fill_ssdt_generator(const struct device *device) |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 412 | { |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 413 | char pscope[] = "\\_SB.PCI0"; |
| 414 | |
| 415 | acpigen_write_scope(pscope); |
Felix Held | e345378 | 2023-04-20 13:06:08 +0200 | [diff] [blame] | 416 | acpigen_write_name_dword("TOM1", get_top_of_mem_below_4gb()); |
| 417 | |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 418 | /* |
| 419 | * Since XP only implements parts of ACPI 2.0, we can't use a qword |
| 420 | * here. |
| 421 | * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt |
| 422 | * slide 22ff. |
| 423 | * Shift value right by 20 bit to make it fit into 32bit, |
| 424 | * giving us 1MB granularity and a limit of almost 4Exabyte of memory. |
| 425 | */ |
Felix Held | 27af3e6 | 2023-04-22 05:59:52 +0200 | [diff] [blame] | 426 | acpigen_write_name_dword("TOM2", get_top_of_mem_above_4gb() >> 20); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 427 | acpigen_pop_len(); |
| 428 | } |
| 429 | |
Furquan Shaikh | 0f007d8 | 2020-04-24 06:41:18 -0700 | [diff] [blame] | 430 | static unsigned long agesa_write_acpi_tables(const struct device *device, |
Alexander Couzens | 83fc32f | 2015-04-12 22:28:37 +0200 | [diff] [blame] | 431 | unsigned long current, |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 432 | acpi_rsdp_t *rsdp) |
| 433 | { |
| 434 | acpi_srat_t *srat; |
| 435 | acpi_slit_t *slit; |
| 436 | acpi_header_t *ssdt; |
| 437 | acpi_header_t *alib; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 438 | acpi_ivrs_t *ivrs; |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 439 | |
| 440 | /* HEST */ |
Elyes Haouas | d6b6b22 | 2022-10-10 12:34:21 +0200 | [diff] [blame] | 441 | current = ALIGN_UP(current, 8); |
Vladimir Serbinenko | 807127f | 2014-11-09 13:36:18 +0100 | [diff] [blame] | 442 | acpi_write_hest((void *)current, acpi_fill_hest); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 443 | acpi_add_table(rsdp, (void *)current); |
| 444 | current += ((acpi_header_t *)current)->length; |
| 445 | |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 446 | /* IVRS */ |
Elyes Haouas | d6b6b22 | 2022-10-10 12:34:21 +0200 | [diff] [blame] | 447 | current = ALIGN_UP(current, 8); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 448 | printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 449 | ivrs = (acpi_ivrs_t *)current; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 450 | acpi_create_ivrs(ivrs, acpi_fill_ivrs); |
| 451 | current += ivrs->header.length; |
| 452 | acpi_add_table(rsdp, ivrs); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 453 | |
| 454 | /* SRAT */ |
Elyes Haouas | d6b6b22 | 2022-10-10 12:34:21 +0200 | [diff] [blame] | 455 | current = ALIGN_UP(current, 8); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 456 | printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 457 | srat = (acpi_srat_t *)agesawrapper_getlateinitptr(PICK_SRAT); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 458 | if (srat != NULL) { |
| 459 | memcpy((void *)current, srat, srat->header.length); |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 460 | srat = (acpi_srat_t *)current; |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 461 | current += srat->header.length; |
| 462 | acpi_add_table(rsdp, srat); |
| 463 | } else { |
| 464 | printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); |
| 465 | } |
| 466 | |
| 467 | /* SLIT */ |
Elyes Haouas | d6b6b22 | 2022-10-10 12:34:21 +0200 | [diff] [blame] | 468 | current = ALIGN_UP(current, 8); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 469 | printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 470 | slit = (acpi_slit_t *)agesawrapper_getlateinitptr(PICK_SLIT); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 471 | if (slit != NULL) { |
| 472 | memcpy((void *)current, slit, slit->header.length); |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 473 | slit = (acpi_slit_t *)current; |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 474 | current += slit->header.length; |
| 475 | acpi_add_table(rsdp, slit); |
| 476 | } else { |
| 477 | printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); |
| 478 | } |
| 479 | |
| 480 | /* ALIB */ |
Elyes Haouas | d6b6b22 | 2022-10-10 12:34:21 +0200 | [diff] [blame] | 481 | current = ALIGN_UP(current, 16); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 482 | printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 483 | alib = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_ALIB); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 484 | if (alib != NULL) { |
| 485 | memcpy((void *)current, alib, alib->length); |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 486 | alib = (acpi_header_t *)current; |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 487 | current += alib->length; |
| 488 | acpi_add_table(rsdp, (void *)alib); |
| 489 | } |
| 490 | else { |
| 491 | printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); |
| 492 | } |
| 493 | |
| 494 | /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */ |
| 495 | /* SSDT */ |
Elyes Haouas | d6b6b22 | 2022-10-10 12:34:21 +0200 | [diff] [blame] | 496 | current = ALIGN_UP(current, 16); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 497 | printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 498 | ssdt = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_PSTATE); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 499 | if (ssdt != NULL) { |
| 500 | memcpy((void *)current, ssdt, ssdt->length); |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 501 | ssdt = (acpi_header_t *)current; |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 502 | current += ssdt->length; |
| 503 | } |
| 504 | else { |
| 505 | printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); |
| 506 | } |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 507 | acpi_add_table(rsdp, ssdt); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 508 | |
| 509 | printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); |
| 510 | return current; |
| 511 | } |
| 512 | |
Felix Held | 7b9c647 | 2023-11-16 16:06:49 +0100 | [diff] [blame] | 513 | struct device_operations amd_pi_northbridge_ops = { |
Michał Żygowski | fb198c6 | 2021-05-09 13:54:09 +0200 | [diff] [blame] | 514 | .read_resources = nb_read_resources, |
Felix Held | b986e21 | 2023-12-16 00:58:09 +0100 | [diff] [blame] | 515 | .set_resources = pci_dev_set_resources, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 516 | .enable_resources = pci_dev_enable_resources, |
| 517 | .init = northbridge_init, |
Michał Żygowski | fb198c6 | 2021-05-09 13:54:09 +0200 | [diff] [blame] | 518 | .ops_pci = &pci_dev_ops_pci, |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 519 | .acpi_fill_ssdt = northbridge_fill_ssdt_generator, |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 520 | .write_acpi_tables = agesa_write_acpi_tables, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 521 | }; |
| 522 | |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 523 | static void fam16_finalize(void *chip_info) |
| 524 | { |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 525 | struct device *dev; |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 526 | dev = pcidev_on_root(0, 0); /* clear IoapicSbFeatureEn */ |
Elyes Haouas | a1f5ad0 | 2022-02-17 18:14:08 +0100 | [diff] [blame] | 527 | |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 528 | pci_write_config32(dev, 0xF8, 0); |
| 529 | pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ |
| 530 | |
Michał Żygowski | 6ca5b47 | 2019-09-10 15:10:22 +0200 | [diff] [blame] | 531 | /* |
| 532 | * Currently it is impossible to enable ACS with AGESA by setting the |
| 533 | * correct bit for AmdInitMid phase. AGESA code path does not call the |
| 534 | * right function that enables these functionalities. Disabled ACS |
| 535 | * result in multiple PCIe devices to be assigned to the same IOMMU |
| 536 | * group. Without IOMMU group separation the devices cannot be passed |
| 537 | * through independently. |
| 538 | */ |
| 539 | |
| 540 | /* Select GPP link core IO Link Strap Control register 0xB0 */ |
| 541 | pci_write_config32(dev, 0xE0, 0x014000B0); |
Michał Żygowski | 6ca5b47 | 2019-09-10 15:10:22 +0200 | [diff] [blame] | 542 | |
| 543 | /* Enable AER (bit 5) and ACS (bit 6 undocumented) */ |
Elyes Haouas | a1f5ad0 | 2022-02-17 18:14:08 +0100 | [diff] [blame] | 544 | pci_or_config32(dev, 0xE4, PCIE_CAP_AER | PCIE_CAP_ACS); |
Michał Żygowski | 6ca5b47 | 2019-09-10 15:10:22 +0200 | [diff] [blame] | 545 | |
| 546 | /* Select GPP link core Wrapper register 0x00 (undocumented) */ |
| 547 | pci_write_config32(dev, 0xE0, 0x01300000); |
Michał Żygowski | 6ca5b47 | 2019-09-10 15:10:22 +0200 | [diff] [blame] | 548 | |
| 549 | /* |
| 550 | * Enable ACS capabilities straps including sub-items. From lspci it |
| 551 | * looks like these bits enable: Source Validation and Translation |
| 552 | * Blocking |
| 553 | */ |
Elyes Haouas | a1f5ad0 | 2022-02-17 18:14:08 +0100 | [diff] [blame] | 554 | pci_or_config32(dev, 0xE4, (BIT(24) | BIT(25) | BIT(26))); |
Michał Żygowski | 6ca5b47 | 2019-09-10 15:10:22 +0200 | [diff] [blame] | 555 | |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 556 | /* disable No Snoop */ |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 557 | dev = pcidev_on_root(1, 1); |
Kyösti Mälkki | 69f6fd4 | 2019-01-21 14:19:01 +0200 | [diff] [blame] | 558 | if (dev != NULL) { |
Elyes Haouas | a1f5ad0 | 2022-02-17 18:14:08 +0100 | [diff] [blame] | 559 | pci_and_config32(dev, 0x60, ~(1 << 11)); |
Kyösti Mälkki | 69f6fd4 | 2019-01-21 14:19:01 +0200 | [diff] [blame] | 560 | } |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 561 | } |
| 562 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 563 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 564 | struct hw_mem_hole_info { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 565 | unsigned int hole_startk; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 566 | int node_id; |
| 567 | }; |
| 568 | static struct hw_mem_hole_info get_hw_mem_hole_info(void) |
| 569 | { |
| 570 | struct hw_mem_hole_info mem_hole; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 571 | mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; |
| 572 | mem_hole.node_id = -1; |
Felix Held | a880720 | 2023-11-16 21:29:33 +0100 | [diff] [blame] | 573 | |
| 574 | resource_t basek, limitk; |
Felix Held | 3eaa850 | 2023-12-16 01:37:34 +0100 | [diff] [blame] | 575 | if (get_dram_base_limit(&basek, &limitk)) { // memory on this node |
Felix Held | a880720 | 2023-11-16 21:29:33 +0100 | [diff] [blame] | 576 | u32 hole = pci_read_config32(get_node_pci(0, 1), 0xf0); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 577 | if (hole & 2) { // we find the hole |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 578 | mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; |
Felix Held | a880720 | 2023-11-16 21:29:33 +0100 | [diff] [blame] | 579 | mem_hole.node_id = 0; // record the node No with hole |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 580 | } |
| 581 | } |
| 582 | return mem_hole; |
| 583 | } |
| 584 | #endif |
| 585 | |
Michał Żygowski | f5d457d | 2021-05-09 13:58:04 +0200 | [diff] [blame] | 586 | static void domain_read_resources(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 587 | { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 588 | unsigned long mmio_basek; |
Felix Held | dcbb1e8 | 2023-12-17 18:20:01 +0100 | [diff] [blame^] | 589 | unsigned long idx = 0; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 590 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 591 | struct hw_mem_hole_info mem_hole; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 592 | #endif |
| 593 | |
Michał Żygowski | f5d457d | 2021-05-09 13:58:04 +0200 | [diff] [blame] | 594 | pci_domain_read_resources(dev); |
| 595 | |
Michał Żygowski | 58d6f96 | 2021-05-05 10:52:08 +0200 | [diff] [blame] | 596 | /* TOP_MEM MSR is our boundary between DRAM and MMIO under 4G */ |
Felix Held | 5e9afe7 | 2023-04-20 12:55:55 +0200 | [diff] [blame] | 597 | mmio_basek = get_top_of_mem_below_4gb() >> 10; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 598 | |
| 599 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 600 | /* if the hw mem hole is already set in raminit stage, here we will compare |
| 601 | * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will |
| 602 | * use hole_basek as mmio_basek and we don't need to reset hole. |
| 603 | * otherwise We reset the hole to the mmio_basek |
| 604 | */ |
| 605 | |
| 606 | mem_hole = get_hw_mem_hole_info(); |
| 607 | |
| 608 | // Use hole_basek as mmio_basek, and we don't need to reset hole anymore |
| 609 | if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { |
| 610 | mmio_basek = mem_hole.hole_startk; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 611 | } |
| 612 | #endif |
| 613 | |
Felix Held | ce8dfc5 | 2023-11-17 17:23:47 +0100 | [diff] [blame] | 614 | resource_t basek, limitk, sizek; |
Felix Held | 3eaa850 | 2023-12-16 01:37:34 +0100 | [diff] [blame] | 615 | if (get_dram_base_limit(&basek, &limitk)) { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 616 | sizek = limitk - basek; |
| 617 | |
Felix Held | ce8dfc5 | 2023-11-17 17:23:47 +0100 | [diff] [blame] | 618 | printk(BIOS_DEBUG, "basek=%08llx, limitk=%08llx, sizek=%08llx,\n", |
| 619 | basek, limitk, sizek); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 620 | |
Elyes Haouas | 5213b19 | 2022-02-25 18:13:03 +0100 | [diff] [blame] | 621 | /* See if we need a hole from 0xa0000 (640K) to 0xfffff (1024K) */ |
Elyes Haouas | 9d8df30 | 2022-02-25 18:23:01 +0100 | [diff] [blame] | 622 | if (basek < 640 && sizek > 1024) { |
Felix Held | dcbb1e8 | 2023-12-17 18:20:01 +0100 | [diff] [blame^] | 623 | ram_resource_kb(dev, idx++, basek, 640 - basek); |
Elyes Haouas | 9d8df30 | 2022-02-25 18:23:01 +0100 | [diff] [blame] | 624 | basek = 1024; |
Michał Żygowski | 58d6f96 | 2021-05-05 10:52:08 +0200 | [diff] [blame] | 625 | sizek = limitk - basek; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 626 | } |
| 627 | |
Felix Held | ce8dfc5 | 2023-11-17 17:23:47 +0100 | [diff] [blame] | 628 | printk(BIOS_DEBUG, "basek=%08llx, limitk=%08llx, sizek=%08llx,\n", |
| 629 | basek, limitk, sizek); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 630 | |
| 631 | /* split the region to accommodate pci memory space */ |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 632 | if ((basek < 4 * 1024 * 1024) && (limitk > mmio_basek)) { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 633 | if (basek <= mmio_basek) { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 634 | unsigned int pre_sizek; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 635 | pre_sizek = mmio_basek - basek; |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 636 | if (pre_sizek > 0) { |
Felix Held | dcbb1e8 | 2023-12-17 18:20:01 +0100 | [diff] [blame^] | 637 | ram_resource_kb(dev, idx++, basek, pre_sizek); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 638 | sizek -= pre_sizek; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 639 | } |
| 640 | basek = mmio_basek; |
| 641 | } |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 642 | if ((basek + sizek) <= 4 * 1024 * 1024) { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 643 | sizek = 0; |
| 644 | } |
| 645 | else { |
Felix Held | 27af3e6 | 2023-04-22 05:59:52 +0200 | [diff] [blame] | 646 | uint64_t topmem2 = get_top_of_mem_above_4gb(); |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 647 | basek = 4 * 1024 * 1024; |
| 648 | sizek = topmem2 / 1024 - basek; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 649 | } |
| 650 | } |
| 651 | |
Felix Held | dcbb1e8 | 2023-12-17 18:20:01 +0100 | [diff] [blame^] | 652 | ram_resource_kb(dev, idx++, basek, sizek); |
Felix Held | ce8dfc5 | 2023-11-17 17:23:47 +0100 | [diff] [blame] | 653 | printk(BIOS_DEBUG, "mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", |
| 654 | mmio_basek, basek, limitk); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 655 | } |
| 656 | |
Felix Held | dcbb1e8 | 2023-12-17 18:20:01 +0100 | [diff] [blame^] | 657 | add_uma_resource_below_tolm(dev, idx++); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 658 | } |
| 659 | |
Aaron Durbin | aa090cb | 2017-09-13 16:01:52 -0600 | [diff] [blame] | 660 | static const char *domain_acpi_name(const struct device *dev) |
Philipp Deppenwiese | 3067012 | 2017-03-01 02:24:33 +0100 | [diff] [blame] | 661 | { |
| 662 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 663 | return "PCI0"; |
| 664 | |
| 665 | return NULL; |
| 666 | } |
| 667 | |
Felix Held | 8ccd314 | 2023-11-16 00:58:30 +0100 | [diff] [blame] | 668 | struct device_operations amd_fam16_mod30_pci_domain_ops = { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 669 | .read_resources = domain_read_resources, |
Michał Żygowski | f5d457d | 2021-05-09 13:58:04 +0200 | [diff] [blame] | 670 | .set_resources = pci_domain_set_resources, |
Arthur Heymans | 0b0113f | 2023-08-31 17:09:28 +0200 | [diff] [blame] | 671 | .scan_bus = pci_host_bridge_scan_bus, |
Philipp Deppenwiese | 3067012 | 2017-03-01 02:24:33 +0100 | [diff] [blame] | 672 | .acpi_name = domain_acpi_name, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 673 | }; |
| 674 | |
Michał Kopeć | dc35d2a | 2021-11-30 17:40:52 +0100 | [diff] [blame] | 675 | void mp_init_cpus(struct bus *cpu_bus) |
| 676 | { |
Arthur Heymans | 4fcaccf | 2022-06-02 13:17:37 +0200 | [diff] [blame] | 677 | extern const struct mp_ops amd_mp_ops_no_smm; |
Michał Kopeć | dc35d2a | 2021-11-30 17:40:52 +0100 | [diff] [blame] | 678 | /* TODO: Handle mp_init_with_smm failure? */ |
Arthur Heymans | 4fcaccf | 2022-06-02 13:17:37 +0200 | [diff] [blame] | 679 | mp_init_with_smm(cpu_bus, &amd_mp_ops_no_smm); |
Michał Kopeć | dc35d2a | 2021-11-30 17:40:52 +0100 | [diff] [blame] | 680 | |
| 681 | /* The flash is now no longer cacheable. Reset to WP for performance. */ |
| 682 | mtrr_use_temp_range(OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE, |
| 683 | MTRR_TYPE_WRPROT); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 684 | } |
| 685 | |
Felix Held | c391bff | 2023-02-16 19:38:49 +0100 | [diff] [blame] | 686 | void generate_cpu_entries(const struct device *device) |
| 687 | { |
| 688 | int cpu; |
| 689 | const int cores = get_cpu_count(); |
| 690 | |
| 691 | printk(BIOS_DEBUG, "ACPI \\_SB report %d core(s)\n", cores); |
| 692 | |
| 693 | /* Generate \_SB.Pxxx */ |
| 694 | for (cpu = 0; cpu < cores; cpu++) { |
| 695 | acpigen_write_processor_device(cpu); |
| 696 | acpigen_write_processor_device_end(); |
| 697 | } |
| 698 | } |
| 699 | |
Felix Held | 8ccd314 | 2023-11-16 00:58:30 +0100 | [diff] [blame] | 700 | struct device_operations amd_fam16_mod30_cpu_bus_ops = { |
Felix Held | c391bff | 2023-02-16 19:38:49 +0100 | [diff] [blame] | 701 | .read_resources = noop_read_resources, |
| 702 | .set_resources = noop_set_resources, |
| 703 | .init = mp_cpu_bus_init, |
| 704 | .acpi_fill_ssdt = generate_cpu_entries, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 705 | }; |
| 706 | |
Felix Held | 1952d13 | 2023-11-16 00:54:30 +0100 | [diff] [blame] | 707 | struct chip_operations northbridge_amd_pi_00730F01_ops = { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 708 | CHIP_NAME("AMD FAM16 Root Complex") |
Felix Held | 1952d13 | 2023-11-16 00:54:30 +0100 | [diff] [blame] | 709 | .final = fam16_finalize, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 710 | }; |
| 711 | |
| 712 | /********************************************************************* |
| 713 | * Change the vendor / device IDs to match the generic VBIOS header. * |
| 714 | *********************************************************************/ |
| 715 | u32 map_oprom_vendev(u32 vendev) |
| 716 | { |
| 717 | u32 new_vendev; |
| 718 | new_vendev = |
| 719 | ((0x10029850 <= vendev) && (vendev <= 0x1002986F)) ? 0x10029850 : vendev; |
| 720 | |
| 721 | if (vendev != new_vendev) |
| 722 | printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", vendev, new_vendev); |
| 723 | |
| 724 | return new_vendev; |
| 725 | } |