efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; version 2 of the License. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 12 | */ |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 13 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 14 | /****************************************************************************** |
| 15 | * AMD Generic Encapsulated Software Architecture |
| 16 | * |
Kyösti Mälkki | 7076aa5 | 2017-09-02 16:20:15 +0300 | [diff] [blame] | 17 | * $Workfile:: cache_as_ram.S |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 18 | * |
Kyösti Mälkki | 7076aa5 | 2017-09-02 16:20:15 +0300 | [diff] [blame] | 19 | * Description: cache_as_ram.S - AGESA Module Entry Point for GCC complier |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 20 | * |
| 21 | ****************************************************************************** |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 22 | */ |
| 23 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 24 | #include "gcccar.inc" |
Kyösti Mälkki | 7076aa5 | 2017-09-02 16:20:15 +0300 | [diff] [blame] | 25 | #include <cpu/x86/post_code.h> |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 26 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 27 | .code32 |
Kyösti Mälkki | 7076aa5 | 2017-09-02 16:20:15 +0300 | [diff] [blame] | 28 | .globl _cache_as_ram_setup, _cache_as_ram_setup_end |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 29 | |
Kyösti Mälkki | 7076aa5 | 2017-09-02 16:20:15 +0300 | [diff] [blame] | 30 | _cache_as_ram_setup: |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 31 | |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame] | 32 | /* Preserve BIST. */ |
| 33 | movd %eax, %mm0 |
Kyösti Mälkki | 1779d53 | 2016-11-23 21:29:26 +0200 | [diff] [blame] | 34 | |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame] | 35 | post_code(0xa0) |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 36 | |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame] | 37 | AMD_ENABLE_STACK |
Kyösti Mälkki | f6fe2f1 | 2016-11-21 11:26:48 +0200 | [diff] [blame] | 38 | |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame] | 39 | /* Align the stack. */ |
| 40 | and $0xFFFFFFF0, %esp |
Kyösti Mälkki | 26929bd | 2016-11-23 20:40:53 +0200 | [diff] [blame] | 41 | |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame] | 42 | /* Must maintain 16-byte stack alignment here. */ |
| 43 | pushl $0x0 |
| 44 | pushl $0x0 |
| 45 | pushl $0x0 |
| 46 | movd %mm0, %eax /* bist */ |
| 47 | pushl %eax |
| 48 | call romstage_main |
Kyösti Mälkki | 63fac81 | 2017-09-02 16:41:43 +0300 | [diff] [blame] | 49 | |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame] | 50 | /* Should never see this postcode */ |
Kyösti Mälkki | 5639736 | 2017-09-07 22:13:10 +0300 | [diff] [blame] | 51 | post_code(0xae) |
Kyösti Mälkki | 63fac81 | 2017-09-02 16:41:43 +0300 | [diff] [blame] | 52 | |
Kyösti Mälkki | ba22e15 | 2016-11-23 06:47:15 +0200 | [diff] [blame] | 53 | stop: |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame] | 54 | hlt |
| 55 | jmp stop |
Kyösti Mälkki | 63fac81 | 2017-09-02 16:41:43 +0300 | [diff] [blame] | 56 | |
Kyösti Mälkki | 7076aa5 | 2017-09-02 16:20:15 +0300 | [diff] [blame] | 57 | _cache_as_ram_setup_end: |