Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | // Use simple device model for this file even in ramstage |
| 17 | #define __SIMPLE_DEVICE__ |
| 18 | |
Kyösti Mälkki | a963acd | 2019-08-16 20:34:25 +0300 | [diff] [blame] | 19 | #include <arch/romstage.h> |
Kyösti Mälkki | cd7a70f | 2019-08-17 20:51:08 +0300 | [diff] [blame] | 20 | #include <commonlib/helpers.h> |
Kyösti Mälkki | e2e1f12 | 2019-08-09 09:34:23 +0300 | [diff] [blame] | 21 | #include <cpu/x86/mtrr.h> |
Kyösti Mälkki | 540151f | 2019-08-15 11:20:18 +0300 | [diff] [blame] | 22 | #include <cpu/x86/smm.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 23 | #include <device/pci_ops.h> |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 24 | #include <cbmem.h> |
| 25 | #include "haswell.h" |
| 26 | |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 27 | static uintptr_t smm_region_start(void) |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 28 | { |
| 29 | /* |
| 30 | * Base of TSEG is top of usable DRAM below 4GiB. The register has |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 31 | * 1 MiB alignment. |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 32 | */ |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 33 | uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); |
| 34 | return tom & ~((1 << 20) - 1); |
| 35 | } |
| 36 | |
| 37 | void *cbmem_top(void) |
| 38 | { |
| 39 | return (void *)smm_region_start(); |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 40 | } |
Kyösti Mälkki | 825646e | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 41 | |
Kyösti Mälkki | 540151f | 2019-08-15 11:20:18 +0300 | [diff] [blame] | 42 | void smm_region(uintptr_t *start, size_t *size) |
Kyösti Mälkki | 825646e | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 43 | { |
Kyösti Mälkki | 540151f | 2019-08-15 11:20:18 +0300 | [diff] [blame] | 44 | *start = smm_region_start(); |
| 45 | *size = CONFIG_SMM_TSEG_SIZE; |
Kyösti Mälkki | 825646e | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 46 | } |
Kyösti Mälkki | e2e1f12 | 2019-08-09 09:34:23 +0300 | [diff] [blame] | 47 | |
Kyösti Mälkki | 5bc641a | 2019-08-09 09:37:49 +0300 | [diff] [blame] | 48 | void fill_postcar_frame(struct postcar_frame *pcf) |
Kyösti Mälkki | e2e1f12 | 2019-08-09 09:34:23 +0300 | [diff] [blame] | 49 | { |
Kyösti Mälkki | e2e1f12 | 2019-08-09 09:34:23 +0300 | [diff] [blame] | 50 | uintptr_t top_of_ram; |
| 51 | |
Kyösti Mälkki | e2e1f12 | 2019-08-09 09:34:23 +0300 | [diff] [blame] | 52 | /* Cache at least 8 MiB below the top of ram, and at most 8 MiB |
| 53 | * above top of the ram. This satisfies MTRR alignment requirement |
| 54 | * with different TSEG size configurations. |
| 55 | */ |
| 56 | top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); |
Kyösti Mälkki | 5bc641a | 2019-08-09 09:37:49 +0300 | [diff] [blame] | 57 | postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, |
Kyösti Mälkki | e2e1f12 | 2019-08-09 09:34:23 +0300 | [diff] [blame] | 58 | MTRR_TYPE_WRBACK); |
Kyösti Mälkki | e2e1f12 | 2019-08-09 09:34:23 +0300 | [diff] [blame] | 59 | } |