Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 4 | #include <acpi/acpi.h> |
Angel Pons | 20905cf | 2020-08-03 14:18:41 +0200 | [diff] [blame] | 5 | #include <commonlib/helpers.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 7 | #include <delay.h> |
| 8 | #include <cpu/intel/model_206ax/model_206ax.h> |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 9 | #include <cpu/x86/msr.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 10 | #include <device/device.h> |
| 11 | #include <device/pci.h> |
| 12 | #include <device/pci_ids.h> |
Angel Pons | 964d91f | 2020-12-07 13:11:17 +0100 | [diff] [blame] | 13 | #include <types.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 14 | #include "chip.h" |
| 15 | #include "sandybridge.h" |
Kyösti Mälkki | f091f4d | 2019-08-14 03:49:21 +0300 | [diff] [blame] | 16 | #include <cpu/intel/smm_reloc.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 17 | |
Kyösti Mälkki | f7bfc34 | 2013-10-18 11:02:46 +0300 | [diff] [blame] | 18 | /* IGD UMA memory */ |
| 19 | static uint64_t uma_memory_base = 0; |
| 20 | static uint64_t uma_memory_size = 0; |
| 21 | |
Angel Pons | 964d91f | 2020-12-07 13:11:17 +0100 | [diff] [blame] | 22 | bool is_sandybridge(void) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 23 | { |
Angel Pons | 964d91f | 2020-12-07 13:11:17 +0100 | [diff] [blame] | 24 | const uint16_t bridge_id = pci_read_config16(pcidev_on_root(0, 0), PCI_DEVICE_ID); |
| 25 | |
| 26 | return (bridge_id & BASE_REV_MASK) == BASE_REV_SNB; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 27 | } |
| 28 | |
| 29 | /* Reserve everything between A segment and 1MB: |
| 30 | * |
| 31 | * 0xa0000 - 0xbffff: legacy VGA |
| 32 | * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) |
| 33 | * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI |
| 34 | */ |
| 35 | static const int legacy_hole_base_k = 0xa0000 / 1024; |
| 36 | static const int legacy_hole_size_k = 384; |
| 37 | |
Angel Pons | 8bf1976 | 2020-08-03 14:55:18 +0200 | [diff] [blame] | 38 | int decode_pcie_bar(u32 *const base, u32 *const len) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 39 | { |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 40 | *base = 0; |
Angel Pons | 20905cf | 2020-08-03 14:18:41 +0200 | [diff] [blame] | 41 | *len = 0; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 42 | |
Angel Pons | 20905cf | 2020-08-03 14:18:41 +0200 | [diff] [blame] | 43 | struct device *dev = pcidev_on_root(0, 0); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 44 | if (!dev) |
| 45 | return 0; |
| 46 | |
Angel Pons | 20905cf | 2020-08-03 14:18:41 +0200 | [diff] [blame] | 47 | const u32 pciexbar_reg = pci_read_config32(dev, PCIEXBAR); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 48 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 49 | /* MMCFG not supported or not enabled */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 50 | if (!(pciexbar_reg & (1 << 0))) |
| 51 | return 0; |
| 52 | |
| 53 | switch ((pciexbar_reg >> 1) & 3) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 54 | case 0: /* 256MB */ |
Angel Pons | 20905cf | 2020-08-03 14:18:41 +0200 | [diff] [blame] | 55 | *base = pciexbar_reg & (0x0f << 28); |
| 56 | *len = 256 * MiB; |
| 57 | return 1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 58 | case 1: /* 128M */ |
Angel Pons | 20905cf | 2020-08-03 14:18:41 +0200 | [diff] [blame] | 59 | *base = pciexbar_reg & (0x1f << 27); |
| 60 | *len = 128 * MiB; |
| 61 | return 1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 62 | case 2: /* 64M */ |
Angel Pons | 20905cf | 2020-08-03 14:18:41 +0200 | [diff] [blame] | 63 | *base = pciexbar_reg & (0x3f << 26); |
| 64 | *len = 64 * MiB; |
| 65 | return 1; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 66 | } |
| 67 | |
| 68 | return 0; |
| 69 | } |
| 70 | |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 71 | static const char *northbridge_acpi_name(const struct device *dev) |
| 72 | { |
| 73 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 74 | return "PCI0"; |
| 75 | |
| 76 | if (dev->path.type != DEVICE_PATH_PCI) |
| 77 | return NULL; |
| 78 | |
| 79 | switch (dev->path.pci.devfn) { |
| 80 | case PCI_DEVFN(0, 0): |
| 81 | return "MCHC"; |
| 82 | } |
| 83 | |
| 84 | return NULL; |
| 85 | } |
| 86 | |
| 87 | /* |
| 88 | * TODO We could determine how many PCIe busses we need in the bar. |
| 89 | * For now, that number is hardcoded to a max of 64. |
| 90 | */ |
| 91 | static struct device_operations pci_domain_ops = { |
| 92 | .read_resources = pci_domain_read_resources, |
| 93 | .set_resources = pci_domain_set_resources, |
| 94 | .scan_bus = pci_domain_scan_bus, |
| 95 | .write_acpi_tables = northbridge_write_acpi_tables, |
| 96 | .acpi_name = northbridge_acpi_name, |
| 97 | }; |
| 98 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 99 | static void add_fixed_resources(struct device *dev, int index) |
| 100 | { |
Kyösti Mälkki | 7f189cc | 2012-07-27 13:12:03 +0300 | [diff] [blame] | 101 | mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 102 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 103 | mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 >> 10) - legacy_hole_base_k); |
| 104 | |
| 105 | reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); |
Kyösti Mälkki | 1ec5e74 | 2012-07-26 23:51:20 +0300 | [diff] [blame] | 106 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 107 | #if CONFIG(CHROMEOS_RAMOOPS) |
Aaron Durbin | c965076 | 2013-03-22 22:03:09 -0500 | [diff] [blame] | 108 | reserved_ram_resource(dev, index++, |
| 109 | CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 110 | CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); |
Kyösti Mälkki | 1ec5e74 | 2012-07-26 23:51:20 +0300 | [diff] [blame] | 111 | #endif |
| 112 | |
Angel Pons | 964d91f | 2020-12-07 13:11:17 +0100 | [diff] [blame] | 113 | if (is_sandybridge()) { |
Nico Huber | 593e7de | 2015-11-04 15:46:00 +0100 | [diff] [blame] | 114 | /* Required for SandyBridge sighting 3715511 */ |
| 115 | bad_ram_resource(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10); |
| 116 | bad_ram_resource(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10); |
| 117 | } |
Nico Huber | bb9469c | 2015-10-21 11:49:23 +0200 | [diff] [blame] | 118 | |
| 119 | /* Reserve IOMMU BARs */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 120 | const u32 capid0_a = pci_read_config32(dev, CAPID0_A); |
Nico Huber | bb9469c | 2015-10-21 11:49:23 +0200 | [diff] [blame] | 121 | if (!(capid0_a & (1 << 23))) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 122 | mmio_resource(dev, index++, GFXVT_BASE >> 10, 4); |
| 123 | mmio_resource(dev, index++, VTVC0_BASE >> 10, 4); |
Nico Huber | bb9469c | 2015-10-21 11:49:23 +0200 | [diff] [blame] | 124 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 125 | } |
| 126 | |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 127 | static void mc_read_resources(struct device *dev) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 128 | { |
Angel Pons | 20905cf | 2020-08-03 14:18:41 +0200 | [diff] [blame] | 129 | u32 pcie_config_base, pcie_config_len; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 130 | uint64_t tom, me_base, touud; |
| 131 | uint32_t tseg_base, uma_size, tolud; |
| 132 | uint16_t ggc; |
| 133 | unsigned long long tomk; |
Angel Pons | 14ea2fc | 2020-05-13 21:46:46 +0200 | [diff] [blame] | 134 | unsigned long index = 3; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 135 | |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 136 | pci_dev_read_resources(dev); |
| 137 | |
Angel Pons | 20905cf | 2020-08-03 14:18:41 +0200 | [diff] [blame] | 138 | if (decode_pcie_bar(&pcie_config_base, &pcie_config_len)) { |
| 139 | const int buses = pcie_config_len / MiB; |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 140 | struct resource *resource = new_resource(dev, PCIEXBAR); |
| 141 | mmconf_resource_init(resource, pcie_config_base, buses); |
| 142 | } |
| 143 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 144 | /* Total Memory 2GB example: |
| 145 | * |
| 146 | * 00000000 0000MB-1992MB 1992MB RAM (writeback) |
| 147 | * 7c800000 1992MB-2000MB 8MB TSEG (SMRR) |
| 148 | * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached) |
| 149 | * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached) |
| 150 | * 7f200000 2034MB TOLUD |
| 151 | * 7f800000 2040MB MEBASE |
| 152 | * 7f800000 2040MB-2048MB 8MB ME UMA (uncached) |
| 153 | * 80000000 2048MB TOM |
| 154 | * 100000000 4096MB-4102MB 6MB RAM (writeback) |
| 155 | * |
| 156 | * Total Memory 4GB example: |
| 157 | * |
| 158 | * 00000000 0000MB-2768MB 2768MB RAM (writeback) |
| 159 | * ad000000 2768MB-2776MB 8MB TSEG (SMRR) |
| 160 | * ad800000 2776MB-2778MB 2MB GFX GTT (uncached) |
| 161 | * ada00000 2778MB-2810MB 32MB GFX UMA (uncached) |
| 162 | * afa00000 2810MB TOLUD |
| 163 | * ff800000 4088MB MEBASE |
| 164 | * ff800000 4088MB-4096MB 8MB ME UMA (uncached) |
| 165 | * 100000000 4096MB TOM |
| 166 | * 100000000 4096MB-5374MB 1278MB RAM (writeback) |
| 167 | * 14fe00000 5368MB TOUUD |
| 168 | */ |
| 169 | |
| 170 | /* Top of Upper Usable DRAM, including remap */ |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 171 | touud = pci_read_config32(dev, TOUUD + 4); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 172 | touud <<= 32; |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 173 | touud |= pci_read_config32(dev, TOUUD); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 174 | |
| 175 | /* Top of Lower Usable DRAM */ |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 176 | tolud = pci_read_config32(dev, TOLUD); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 177 | |
| 178 | /* Top of Memory - does not account for any UMA */ |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 179 | tom = pci_read_config32(dev, TOM + 4); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 180 | tom <<= 32; |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 181 | tom |= pci_read_config32(dev, TOM); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 182 | |
| 183 | printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", |
| 184 | touud, tolud, tom); |
| 185 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 186 | /* ME UMA needs excluding if total memory < 4GB */ |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 187 | me_base = pci_read_config32(dev, MESEG_BASE + 4); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 188 | me_base <<= 32; |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 189 | me_base |= pci_read_config32(dev, MESEG_BASE); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 190 | |
| 191 | printk(BIOS_DEBUG, "MEBASE 0x%llx\n", me_base); |
| 192 | |
Patrick Rudolph | 240766a | 2015-10-15 15:33:25 +0200 | [diff] [blame] | 193 | uma_memory_base = tolud; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 194 | tomk = tolud >> 10; |
| 195 | if (me_base == tolud) { |
| 196 | /* ME is from MEBASE-TOM */ |
| 197 | uma_size = (tom - me_base) >> 10; |
| 198 | /* Increment TOLUD to account for ME as RAM */ |
| 199 | tolud += uma_size << 10; |
| 200 | /* UMA starts at old TOLUD */ |
| 201 | uma_memory_base = tomk * 1024ULL; |
| 202 | uma_memory_size = uma_size * 1024ULL; |
| 203 | printk(BIOS_DEBUG, "ME UMA base 0x%llx size %uM\n", |
| 204 | me_base, uma_size >> 10); |
| 205 | } |
| 206 | |
| 207 | /* Graphics memory comes next */ |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 208 | ggc = pci_read_config16(dev, GGC); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 209 | if (!(ggc & 2)) { |
| 210 | printk(BIOS_DEBUG, "IGD decoded, subtracting "); |
| 211 | |
| 212 | /* Graphics memory */ |
| 213 | uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL; |
| 214 | printk(BIOS_DEBUG, "%uM UMA", uma_size >> 10); |
| 215 | tomk -= uma_size; |
| 216 | uma_memory_base = tomk * 1024ULL; |
| 217 | uma_memory_size += uma_size * 1024ULL; |
| 218 | |
| 219 | /* GTT Graphics Stolen Memory Size (GGMS) */ |
| 220 | uma_size = ((ggc >> 8) & 0x3) * 1024ULL; |
| 221 | tomk -= uma_size; |
| 222 | uma_memory_base = tomk * 1024ULL; |
| 223 | uma_memory_size += uma_size * 1024ULL; |
| 224 | printk(BIOS_DEBUG, " and %uM GTT\n", uma_size >> 10); |
| 225 | } |
| 226 | |
| 227 | /* Calculate TSEG size from its base which must be below GTT */ |
Aaron Durbin | 1ca2433 | 2020-05-13 11:38:35 -0600 | [diff] [blame] | 228 | tseg_base = pci_read_config32(dev, TSEGMB); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 229 | uma_size = (uma_memory_base - tseg_base) >> 10; |
| 230 | tomk -= uma_size; |
| 231 | uma_memory_base = tomk * 1024ULL; |
| 232 | uma_memory_size += uma_size * 1024ULL; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 233 | printk(BIOS_DEBUG, "TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 234 | |
| 235 | printk(BIOS_INFO, "Available memory below 4GB: %lluM\n", tomk >> 10); |
| 236 | |
| 237 | /* Report the memory regions */ |
Angel Pons | 14ea2fc | 2020-05-13 21:46:46 +0200 | [diff] [blame] | 238 | ram_resource(dev, index++, 0, legacy_hole_base_k); |
| 239 | ram_resource(dev, index++, legacy_hole_base_k + legacy_hole_size_k, |
| 240 | (tomk - (legacy_hole_base_k + legacy_hole_size_k))); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 241 | |
| 242 | /* |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 243 | * If >= 4GB installed, then memory from TOLUD to 4GB is remapped above TOM. |
| 244 | * TOUUD will account for both memory chunks. |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 245 | */ |
| 246 | touud >>= 10; /* Convert to KB */ |
| 247 | if (touud > 4096 * 1024) { |
Angel Pons | 14ea2fc | 2020-05-13 21:46:46 +0200 | [diff] [blame] | 248 | ram_resource(dev, index++, 4096 * 1024, touud - (4096 * 1024)); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 249 | printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", (touud >> 10) - 4096); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 250 | } |
| 251 | |
Angel Pons | 14ea2fc | 2020-05-13 21:46:46 +0200 | [diff] [blame] | 252 | add_fixed_resources(dev, index++); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 253 | } |
| 254 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 255 | static void northbridge_dmi_init(struct device *dev) |
| 256 | { |
Angel Pons | 964d91f | 2020-12-07 13:11:17 +0100 | [diff] [blame] | 257 | const bool is_sandy = is_sandybridge(); |
| 258 | |
Angel Pons | 77516ca | 2020-12-10 16:43:25 +0100 | [diff] [blame] | 259 | const u8 stepping = cpu_stepping(); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 260 | |
Angel Pons | 77516ca | 2020-12-10 16:43:25 +0100 | [diff] [blame] | 261 | u32 reg32; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 262 | |
| 263 | /* Steps prior to DMI ASPM */ |
Angel Pons | 964d91f | 2020-12-07 13:11:17 +0100 | [diff] [blame] | 264 | if (is_sandy) { |
Vincent Palatin | 0ff99b7 | 2012-03-28 16:10:29 -0700 | [diff] [blame] | 265 | reg32 = DMIBAR32(0x250); |
Angel Pons | 77516ca | 2020-12-10 16:43:25 +0100 | [diff] [blame] | 266 | reg32 &= ~(7 << 20); |
| 267 | reg32 |= (2 << 20); |
Vincent Palatin | 0ff99b7 | 2012-03-28 16:10:29 -0700 | [diff] [blame] | 268 | DMIBAR32(0x250) = reg32; |
| 269 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 270 | |
Angel Pons | f950a7e | 2020-09-14 17:15:37 +0200 | [diff] [blame] | 271 | reg32 = DMIBAR32(DMILLTC); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 272 | reg32 |= (1 << 29); |
Angel Pons | f950a7e | 2020-09-14 17:15:37 +0200 | [diff] [blame] | 273 | DMIBAR32(DMILLTC) = reg32; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 274 | |
Angel Pons | 77516ca | 2020-12-10 16:43:25 +0100 | [diff] [blame] | 275 | if (is_sandy && stepping == SNB_STEP_C0) { |
| 276 | reg32 = DMIBAR32(0xbc8); |
| 277 | reg32 &= ~(0xfff << 7); |
| 278 | reg32 |= (0x7d3 << 7); |
| 279 | DMIBAR32(0xbc8) = reg32; |
| 280 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 281 | |
Angel Pons | 77516ca | 2020-12-10 16:43:25 +0100 | [diff] [blame] | 282 | if (!is_sandy || stepping >= SNB_STEP_D1) { |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 283 | reg32 = DMIBAR32(0x1f8); |
| 284 | reg32 &= ~(1 << 26); |
| 285 | reg32 |= (1 << 16); |
| 286 | DMIBAR32(0x1f8) = reg32; |
| 287 | |
| 288 | reg32 = DMIBAR32(0x1fc); |
| 289 | reg32 |= (1 << 12) | (1 << 23); |
| 290 | DMIBAR32(0x1fc) = reg32; |
Angel Pons | 77516ca | 2020-12-10 16:43:25 +0100 | [diff] [blame] | 291 | |
| 292 | } else if (stepping >= SNB_STEP_D0) { |
| 293 | reg32 = DMIBAR32(0x1f8); |
| 294 | reg32 |= (1 << 16); |
| 295 | DMIBAR32(0x1f8) = reg32; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 296 | } |
| 297 | |
Angel Pons | 77516ca | 2020-12-10 16:43:25 +0100 | [diff] [blame] | 298 | /* Clear error status bits */ |
| 299 | DMIBAR32(DMIUESTS) = 0xffffffff; |
| 300 | DMIBAR32(DMICESTS) = 0xffffffff; |
| 301 | |
| 302 | if (!is_sandy) |
| 303 | DMIBAR32(0xc34) = 0xffffffff; |
| 304 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 305 | /* Enable ASPM on SNB link, should happen before PCH link */ |
Angel Pons | 964d91f | 2020-12-07 13:11:17 +0100 | [diff] [blame] | 306 | if (is_sandy) { |
Vincent Palatin | 0ff99b7 | 2012-03-28 16:10:29 -0700 | [diff] [blame] | 307 | reg32 = DMIBAR32(0xd04); |
| 308 | reg32 |= (1 << 4); |
| 309 | DMIBAR32(0xd04) = reg32; |
| 310 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 311 | |
Angel Pons | f950a7e | 2020-09-14 17:15:37 +0200 | [diff] [blame] | 312 | reg32 = DMIBAR32(DMILCTL); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 313 | reg32 |= (1 << 1) | (1 << 0); |
Angel Pons | f950a7e | 2020-09-14 17:15:37 +0200 | [diff] [blame] | 314 | DMIBAR32(DMILCTL) = reg32; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 315 | } |
| 316 | |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 317 | /* Disable unused PEG devices based on devicetree */ |
| 318 | static void disable_peg(void) |
| 319 | { |
| 320 | struct device *dev; |
| 321 | u32 reg; |
| 322 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 323 | dev = pcidev_on_root(0, 0); |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 324 | reg = pci_read_config32(dev, DEVEN); |
| 325 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 326 | dev = pcidev_on_root(1, 2); |
Nico Huber | 2dc15e9 | 2016-02-04 18:59:48 +0100 | [diff] [blame] | 327 | if (!dev || !dev->enabled) { |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 328 | printk(BIOS_DEBUG, "Disabling PEG12.\n"); |
| 329 | reg &= ~DEVEN_PEG12; |
| 330 | } |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 331 | dev = pcidev_on_root(1, 1); |
Nico Huber | 2dc15e9 | 2016-02-04 18:59:48 +0100 | [diff] [blame] | 332 | if (!dev || !dev->enabled) { |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 333 | printk(BIOS_DEBUG, "Disabling PEG11.\n"); |
| 334 | reg &= ~DEVEN_PEG11; |
| 335 | } |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 336 | dev = pcidev_on_root(1, 0); |
Nico Huber | 2dc15e9 | 2016-02-04 18:59:48 +0100 | [diff] [blame] | 337 | if (!dev || !dev->enabled) { |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 338 | printk(BIOS_DEBUG, "Disabling PEG10.\n"); |
| 339 | reg &= ~DEVEN_PEG10; |
| 340 | } |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 341 | dev = pcidev_on_root(2, 0); |
Nico Huber | 2dc15e9 | 2016-02-04 18:59:48 +0100 | [diff] [blame] | 342 | if (!dev || !dev->enabled) { |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 343 | printk(BIOS_DEBUG, "Disabling IGD.\n"); |
| 344 | reg &= ~DEVEN_IGD; |
| 345 | } |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 346 | dev = pcidev_on_root(4, 0); |
Patrick Rudolph | ecd4be8 | 2017-05-14 12:40:50 +0200 | [diff] [blame] | 347 | if (!dev || !dev->enabled) { |
| 348 | printk(BIOS_DEBUG, "Disabling Device 4.\n"); |
| 349 | reg &= ~DEVEN_D4EN; |
| 350 | } |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 351 | dev = pcidev_on_root(6, 0); |
Nico Huber | 2dc15e9 | 2016-02-04 18:59:48 +0100 | [diff] [blame] | 352 | if (!dev || !dev->enabled) { |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 353 | printk(BIOS_DEBUG, "Disabling PEG60.\n"); |
| 354 | reg &= ~DEVEN_PEG60; |
| 355 | } |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 356 | dev = pcidev_on_root(7, 0); |
Patrick Rudolph | ecd4be8 | 2017-05-14 12:40:50 +0200 | [diff] [blame] | 357 | if (!dev || !dev->enabled) { |
| 358 | printk(BIOS_DEBUG, "Disabling Device 7.\n"); |
| 359 | reg &= ~DEVEN_D7EN; |
| 360 | } |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 361 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 362 | dev = pcidev_on_root(0, 0); |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 363 | pci_write_config32(dev, DEVEN, reg); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 364 | |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 365 | if (!(reg & (DEVEN_PEG60 | DEVEN_PEG10 | DEVEN_PEG11 | DEVEN_PEG12))) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 366 | /* |
| 367 | * Set the PEG clock gating bit. Disables the IO clock on all PEG devices. |
| 368 | * |
Angel Pons | 78b43c8 | 2020-03-17 23:55:18 +0100 | [diff] [blame] | 369 | * FIXME: Never clock gate on Ivy Bridge stepping A0! |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 370 | */ |
| 371 | MCHBAR32_OR(PEGCTL, 1); |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 372 | printk(BIOS_DEBUG, "Disabling PEG IO clock.\n"); |
Angel Pons | 78b43c8 | 2020-03-17 23:55:18 +0100 | [diff] [blame] | 373 | } else { |
| 374 | MCHBAR32_AND(PEGCTL, ~1); |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 375 | } |
| 376 | } |
| 377 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 378 | static void northbridge_init(struct device *dev) |
| 379 | { |
| 380 | u8 bios_reset_cpl; |
Duncan Laurie | fe7b5d2 | 2012-06-23 20:14:07 -0700 | [diff] [blame] | 381 | u32 bridge_type; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 382 | |
| 383 | northbridge_dmi_init(dev); |
| 384 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 385 | bridge_type = MCHBAR32(SAPMTIMERS); |
Duncan Laurie | fe7b5d2 | 2012-06-23 20:14:07 -0700 | [diff] [blame] | 386 | bridge_type &= ~0xff; |
| 387 | |
Angel Pons | 964d91f | 2020-12-07 13:11:17 +0100 | [diff] [blame] | 388 | if (is_sandybridge()) { |
| 389 | /* 20h for Sandybridge */ |
| 390 | bridge_type |= 0x20; |
| 391 | } else { |
Duncan Laurie | fe7b5d2 | 2012-06-23 20:14:07 -0700 | [diff] [blame] | 392 | /* Enable Power Aware Interrupt Routing */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 393 | u8 pair = MCHBAR8(INTRDIRCTL); |
| 394 | pair &= ~0x0f; /* Clear 3:0 */ |
| 395 | pair |= 0x04; /* Fixed Priority */ |
| 396 | MCHBAR8(INTRDIRCTL) = pair; |
Duncan Laurie | fe7b5d2 | 2012-06-23 20:14:07 -0700 | [diff] [blame] | 397 | |
| 398 | /* 30h for IvyBridge */ |
| 399 | bridge_type |= 0x30; |
Duncan Laurie | fe7b5d2 | 2012-06-23 20:14:07 -0700 | [diff] [blame] | 400 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 401 | MCHBAR32(SAPMTIMERS) = bridge_type; |
Duncan Laurie | fe7b5d2 | 2012-06-23 20:14:07 -0700 | [diff] [blame] | 402 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 403 | /* Turn off unused devices. Has to be done before setting BIOS_RESET_CPL. */ |
Patrick Rudolph | aad34cd | 2015-10-21 18:05:01 +0200 | [diff] [blame] | 404 | disable_peg(); |
| 405 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 406 | /* |
| 407 | * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU |
| 408 | * that BIOS has initialized memory and power management |
| 409 | */ |
| 410 | bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); |
| 411 | bios_reset_cpl |= 1; |
| 412 | MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; |
| 413 | printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); |
| 414 | |
| 415 | /* Configure turbo power limits 1ms after reset complete bit */ |
| 416 | mdelay(1); |
| 417 | set_power_limits(28); |
| 418 | |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 419 | /* |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 420 | * CPUs with configurable TDP also need power limits set in MCHBAR. |
| 421 | * Use the same values from MSR_PKG_POWER_LIMIT. |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 422 | */ |
| 423 | if (cpu_config_tdp_levels()) { |
| 424 | msr_t msr = rdmsr(MSR_PKG_POWER_LIMIT); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 425 | MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = msr.lo; |
| 426 | MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = msr.hi; |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 427 | } |
| 428 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 429 | /* Set here before graphics PM init */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 430 | MCHBAR32(PAVP_MSG) = 0x00100001; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 431 | } |
| 432 | |
Vladimir Serbinenko | c16e9dfa | 2015-05-29 16:18:01 +0200 | [diff] [blame] | 433 | void northbridge_write_smram(u8 smram) |
| 434 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 435 | pci_write_config8(pcidev_on_root(0, 0), SMRAM, smram); |
Vladimir Serbinenko | c16e9dfa | 2015-05-29 16:18:01 +0200 | [diff] [blame] | 436 | } |
| 437 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 438 | static struct device_operations mc_ops = { |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 439 | .read_resources = mc_read_resources, |
| 440 | .set_resources = pci_dev_set_resources, |
| 441 | .enable_resources = pci_dev_enable_resources, |
| 442 | .init = northbridge_init, |
Angel Pons | 1fc0edd | 2020-05-31 00:03:28 +0200 | [diff] [blame] | 443 | .ops_pci = &pci_dev_ops_pci, |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 444 | .acpi_fill_ssdt = generate_cpu_entries, |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 445 | }; |
| 446 | |
Jonathan A. Kollasch | bda161b | 2020-02-13 13:04:48 -0600 | [diff] [blame] | 447 | static const unsigned short pci_device_ids[] = { |
Jonathan A. Kollasch | d346a19 | 2020-02-11 09:03:48 -0600 | [diff] [blame] | 448 | 0x0100, 0x0104, 0x0108, /* Sandy Bridge */ |
Jonathan A. Kollasch | bda161b | 2020-02-13 13:04:48 -0600 | [diff] [blame] | 449 | 0x0150, 0x0154, 0x0158, /* Ivy Bridge */ |
| 450 | 0 |
Walter Murphy | 496f4a0 | 2012-04-23 11:08:03 -0700 | [diff] [blame] | 451 | }; |
| 452 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 453 | static const struct pci_driver mc_driver __pci_driver = { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 454 | .ops = &mc_ops, |
| 455 | .vendor = PCI_VENDOR_ID_INTEL, |
Jonathan A. Kollasch | bda161b | 2020-02-13 13:04:48 -0600 | [diff] [blame] | 456 | .devices = pci_device_ids, |
Vagiz Trakhanov | 1dd448c | 2017-09-28 14:42:11 +0000 | [diff] [blame] | 457 | }; |
| 458 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 459 | static struct device_operations cpu_bus_ops = { |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame] | 460 | .read_resources = noop_read_resources, |
| 461 | .set_resources = noop_set_resources, |
Kyösti Mälkki | b3267e0 | 2019-08-13 16:44:04 +0300 | [diff] [blame] | 462 | .init = mp_cpu_bus_init, |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 463 | }; |
| 464 | |
Elyes HAOUAS | ab8743c | 2018-02-09 08:21:40 +0100 | [diff] [blame] | 465 | static void enable_dev(struct device *dev) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 466 | { |
| 467 | /* Set the operations if it is a special bus type */ |
Stefan Reinauer | 4aff445 | 2013-02-12 14:17:15 -0800 | [diff] [blame] | 468 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 469 | dev->ops = &pci_domain_ops; |
Stefan Reinauer | 0aa37c4 | 2013-02-12 15:20:54 -0800 | [diff] [blame] | 470 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 471 | dev->ops = &cpu_bus_ops; |
| 472 | } |
| 473 | } |
| 474 | |
| 475 | struct chip_operations northbridge_intel_sandybridge_ops = { |
Damien Zammit | 3517038 | 2014-10-29 00:11:53 +1100 | [diff] [blame] | 476 | CHIP_NAME("Intel SandyBridge/IvyBridge integrated Northbridge") |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 477 | .enable_dev = enable_dev, |
| 478 | }; |