Felix Held | 926887c | 2023-10-13 21:19:53 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
Felix Held | 474c5d6 | 2024-01-09 16:56:56 +0100 | [diff] [blame] | 3 | #include <amdblocks/ioapic.h> |
Felix Held | 926887c | 2023-10-13 21:19:53 +0200 | [diff] [blame] | 4 | #include <amdblocks/data_fabric.h> |
| 5 | #include <amdblocks/root_complex.h> |
| 6 | #include <amdblocks/smn.h> |
| 7 | #include <arch/ioapic.h> |
| 8 | #include <console/console.h> |
| 9 | #include <device/device.h> |
| 10 | #include <types.h> |
| 11 | |
Felix Held | 2f58bbd | 2023-12-07 22:04:13 +0100 | [diff] [blame] | 12 | #include <vendorcode/amd/opensil/genoa_poc/opensil.h> |
| 13 | |
Felix Held | 926887c | 2023-10-13 21:19:53 +0200 | [diff] [blame] | 14 | #define IOHC_IOAPIC_BASE_ADDR_LO 0x2f0 |
| 15 | |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame^] | 16 | void read_soc_memmap_resources(struct device *domain, unsigned long *idx) |
Felix Held | 2f58bbd | 2023-12-07 22:04:13 +0100 | [diff] [blame] | 17 | { |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame^] | 18 | *idx = add_opensil_memmap(domain, *idx); |
Felix Held | 2f58bbd | 2023-12-07 22:04:13 +0100 | [diff] [blame] | 19 | } |
| 20 | |
Felix Held | 926887c | 2023-10-13 21:19:53 +0200 | [diff] [blame] | 21 | static void genoa_domain_set_resources(struct device *domain) |
| 22 | { |
Arthur Heymans | 7fcd4d5 | 2023-08-24 15:12:19 +0200 | [diff] [blame] | 23 | if (domain->downstream->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { |
Felix Held | 926887c | 2023-10-13 21:19:53 +0200 | [diff] [blame] | 24 | printk(BIOS_DEBUG, "Setting VGA decoding for domain 0x%x\n", |
| 25 | domain->path.domain.domain); |
| 26 | const union df_vga_en vga_en = { |
| 27 | .ve = 1, |
| 28 | .dst_fabric_id = get_iohc_fabric_id(domain), |
| 29 | }; |
| 30 | data_fabric_broadcast_write32(DF_VGA_EN, vga_en.raw); |
| 31 | } |
| 32 | |
| 33 | pci_domain_set_resources(domain); |
| 34 | |
| 35 | /* Enable IOAPIC memory decoding */ |
| 36 | struct resource *res = probe_resource(domain, IOMMU_IOAPIC_IDX); |
| 37 | if (res) { |
| 38 | const uint32_t iohc_misc_base = get_iohc_misc_smn_base(domain); |
| 39 | uint32_t ioapic_base = smn_read32(iohc_misc_base | IOHC_IOAPIC_BASE_ADDR_LO); |
| 40 | ioapic_base |= (1 << 0); |
| 41 | smn_write32(iohc_misc_base | IOHC_IOAPIC_BASE_ADDR_LO, ioapic_base); |
| 42 | } |
| 43 | } |
| 44 | |
Felix Held | dd032e0 | 2023-12-12 16:55:52 +0100 | [diff] [blame] | 45 | static void genoa_domain_init(struct device *domain) |
| 46 | { |
| 47 | struct resource *res = probe_resource(domain, IOMMU_IOAPIC_IDX); |
| 48 | if (!res) |
| 49 | return; |
| 50 | |
| 51 | register_new_ioapic((void *)(uintptr_t)res->base); |
| 52 | } |
| 53 | |
Felix Held | 020d4b6 | 2023-12-12 18:45:06 +0100 | [diff] [blame] | 54 | static const char *genoa_domain_acpi_name(const struct device *domain) |
| 55 | { |
| 56 | const char *domain_acpi_names[4] = { |
| 57 | "S0B0", |
| 58 | "S0B1", |
| 59 | "S0B2", |
| 60 | "S0B3", |
| 61 | }; |
| 62 | |
| 63 | if (domain->path.domain.domain < ARRAY_SIZE(domain_acpi_names)) |
| 64 | return domain_acpi_names[domain->path.domain.domain]; |
| 65 | |
| 66 | return NULL; |
| 67 | } |
| 68 | |
Felix Held | 926887c | 2023-10-13 21:19:53 +0200 | [diff] [blame] | 69 | struct device_operations genoa_pci_domain_ops = { |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame^] | 70 | .read_resources = amd_pci_domain_read_resources, |
Felix Held | 0fe8643 | 2023-12-12 19:59:14 +0100 | [diff] [blame] | 71 | .set_resources = genoa_domain_set_resources, |
| 72 | .scan_bus = amd_pci_domain_scan_bus, |
Felix Held | dd032e0 | 2023-12-12 16:55:52 +0100 | [diff] [blame] | 73 | .init = genoa_domain_init, |
Felix Held | 020d4b6 | 2023-12-12 18:45:06 +0100 | [diff] [blame] | 74 | .acpi_name = genoa_domain_acpi_name, |
| 75 | .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, |
Felix Held | 926887c | 2023-10-13 21:19:53 +0200 | [diff] [blame] | 76 | }; |