soc/amd/genoa: Parse APOB for DRAM layout
Use the xPRF call to report holes in memory and report those regions as
reserved.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5605499e39931e1a1592318310112666f8a0f144
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
diff --git a/src/soc/amd/genoa/domain.c b/src/soc/amd/genoa/domain.c
index 43e436a..e428230 100644
--- a/src/soc/amd/genoa/domain.c
+++ b/src/soc/amd/genoa/domain.c
@@ -8,8 +8,22 @@
#include <device/device.h>
#include <types.h>
+#include <vendorcode/amd/opensil/genoa_poc/opensil.h>
+
#define IOHC_IOAPIC_BASE_ADDR_LO 0x2f0
+static void genoa_domain_read_resources(struct device *domain)
+{
+ amd_pci_domain_read_resources(domain);
+
+ // We only want to add the DRAM memory map once
+ if (domain->link_list->secondary == 0) {
+ /* 0x1000 is a large enough first index to be sure to not overlap with the
+ resources added by amd_pci_domain_read_resources */
+ add_opensil_memmap(domain, 0x1000);
+ }
+}
+
static void genoa_domain_set_resources(struct device *domain)
{
if (domain->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
@@ -35,7 +49,7 @@
}
struct device_operations genoa_pci_domain_ops = {
- .read_resources = amd_pci_domain_read_resources,
+ .read_resources = genoa_domain_read_resources,
.set_resources = genoa_domain_set_resources,
.scan_bus = amd_pci_domain_scan_bus,
};