blob: 8ed95abe34c313dd95d832290309d7dcb381faca [file] [log] [blame]
Felix Held926887c2023-10-13 21:19:53 +02001/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <amdblocks/data_fabric.h>
4#include <amdblocks/root_complex.h>
5#include <amdblocks/smn.h>
6#include <arch/ioapic.h>
7#include <console/console.h>
8#include <device/device.h>
9#include <types.h>
10
Felix Held2f58bbd2023-12-07 22:04:13 +010011#include <vendorcode/amd/opensil/genoa_poc/opensil.h>
12
Felix Held926887c2023-10-13 21:19:53 +020013#define IOHC_IOAPIC_BASE_ADDR_LO 0x2f0
14
Felix Held2f58bbd2023-12-07 22:04:13 +010015static void genoa_domain_read_resources(struct device *domain)
16{
17 amd_pci_domain_read_resources(domain);
18
19 // We only want to add the DRAM memory map once
20 if (domain->link_list->secondary == 0) {
21 /* 0x1000 is a large enough first index to be sure to not overlap with the
22 resources added by amd_pci_domain_read_resources */
23 add_opensil_memmap(domain, 0x1000);
24 }
25}
26
Felix Held926887c2023-10-13 21:19:53 +020027static void genoa_domain_set_resources(struct device *domain)
28{
29 if (domain->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
30 printk(BIOS_DEBUG, "Setting VGA decoding for domain 0x%x\n",
31 domain->path.domain.domain);
32 const union df_vga_en vga_en = {
33 .ve = 1,
34 .dst_fabric_id = get_iohc_fabric_id(domain),
35 };
36 data_fabric_broadcast_write32(DF_VGA_EN, vga_en.raw);
37 }
38
39 pci_domain_set_resources(domain);
40
41 /* Enable IOAPIC memory decoding */
42 struct resource *res = probe_resource(domain, IOMMU_IOAPIC_IDX);
43 if (res) {
44 const uint32_t iohc_misc_base = get_iohc_misc_smn_base(domain);
45 uint32_t ioapic_base = smn_read32(iohc_misc_base | IOHC_IOAPIC_BASE_ADDR_LO);
46 ioapic_base |= (1 << 0);
47 smn_write32(iohc_misc_base | IOHC_IOAPIC_BASE_ADDR_LO, ioapic_base);
48 }
49}
50
Felix Helddd032e02023-12-12 16:55:52 +010051static void genoa_domain_init(struct device *domain)
52{
53 struct resource *res = probe_resource(domain, IOMMU_IOAPIC_IDX);
54 if (!res)
55 return;
56
57 register_new_ioapic((void *)(uintptr_t)res->base);
58}
59
Felix Held020d4b62023-12-12 18:45:06 +010060static const char *genoa_domain_acpi_name(const struct device *domain)
61{
62 const char *domain_acpi_names[4] = {
63 "S0B0",
64 "S0B1",
65 "S0B2",
66 "S0B3",
67 };
68
69 if (domain->path.domain.domain < ARRAY_SIZE(domain_acpi_names))
70 return domain_acpi_names[domain->path.domain.domain];
71
72 return NULL;
73}
74
Felix Held926887c2023-10-13 21:19:53 +020075struct device_operations genoa_pci_domain_ops = {
Felix Held0fe86432023-12-12 19:59:14 +010076 .read_resources = genoa_domain_read_resources,
77 .set_resources = genoa_domain_set_resources,
78 .scan_bus = amd_pci_domain_scan_bus,
Felix Helddd032e02023-12-12 16:55:52 +010079 .init = genoa_domain_init,
Felix Held020d4b62023-12-12 18:45:06 +010080 .acpi_name = genoa_domain_acpi_name,
81 .acpi_fill_ssdt = amd_pci_domain_fill_ssdt,
Felix Held926887c2023-10-13 21:19:53 +020082};