Angel Pons | f23ae0b | 2020-04-02 23:48:12 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Kyösti Mälkki | 48518f0 | 2014-11-25 14:20:57 +0200 | [diff] [blame] | 2 | |
Felix Held | 928a9c8 | 2022-02-24 00:51:11 +0100 | [diff] [blame] | 3 | #include <arch/hpet.h> |
Kyösti Mälkki | 48518f0 | 2014-11-25 14:20:57 +0200 | [diff] [blame] | 4 | #include <cpu/x86/mtrr.h> |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 5 | #include <cpu/amd/msr.h> |
Elyes HAOUAS | 8a64370 | 2018-10-23 17:10:27 +0200 | [diff] [blame] | 6 | #include <cpu/amd/mtrr.h> |
Kyösti Mälkki | d610c58 | 2017-03-05 06:28:18 +0200 | [diff] [blame] | 7 | #include <northbridge/amd/agesa/agesa_helper.h> |
| 8 | #include <AGESA.h> |
Elyes HAOUAS | 19f5ba8 | 2018-10-14 14:52:06 +0200 | [diff] [blame] | 9 | #include <amdlib.h> |
Kyösti Mälkki | 48518f0 | 2014-11-25 14:20:57 +0200 | [diff] [blame] | 10 | |
Kyösti Mälkki | 48518f0 | 2014-11-25 14:20:57 +0200 | [diff] [blame] | 11 | void amd_initcpuio(void) |
| 12 | { |
| 13 | UINT64 MsrReg; |
| 14 | UINT32 PciData; |
| 15 | PCI_ADDR PciAddress; |
| 16 | AMD_CONFIG_PARAMS StdHeader; |
| 17 | |
| 18 | /* Enable legacy video routing: D18F1xF4 VGA Enable */ |
| 19 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4); |
| 20 | PciData = 1; |
| 21 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 22 | |
| 23 | /* The platform BIOS needs to ensure the memory ranges of SB800 legacy |
| 24 | * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are |
| 25 | * set to non-posted regions. |
| 26 | */ |
| 27 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); |
| 28 | PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000 |
| 29 | PciData |= 1 << 7; // set NP (non-posted) bit |
| 30 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 31 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); |
Felix Held | 928a9c8 | 2022-02-24 00:51:11 +0100 | [diff] [blame] | 32 | PciData = (HPET_BASE_ADDRESS >> 8) | 3; // lowest NP address is HPET at FED00000 |
Kyösti Mälkki | 48518f0 | 2014-11-25 14:20:57 +0200 | [diff] [blame] | 33 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 34 | |
| 35 | /* Map the remaining PCI hole as posted MMIO */ |
| 36 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); |
| 37 | PciData = 0x00FECF00; // last address before non-posted range |
| 38 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
Elyes HAOUAS | 8a64370 | 2018-10-23 17:10:27 +0200 | [diff] [blame] | 39 | LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader); |
Kyösti Mälkki | 48518f0 | 2014-11-25 14:20:57 +0200 | [diff] [blame] | 40 | MsrReg = (MsrReg >> 8) | 3; |
| 41 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); |
Elyes Haouas | 287048a | 2022-05-29 15:44:11 +0200 | [diff] [blame^] | 42 | PciData = (UINT32)MsrReg; |
Kyösti Mälkki | 48518f0 | 2014-11-25 14:20:57 +0200 | [diff] [blame] | 43 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 44 | |
| 45 | /* Send all IO (0000-FFFF) to southbridge. */ |
| 46 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4); |
| 47 | PciData = 0x0000F000; |
| 48 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 49 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0); |
| 50 | PciData = 0x00000003; |
| 51 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 52 | } |
| 53 | |
Kyösti Mälkki | 4a08e15 | 2014-12-14 19:41:54 +0200 | [diff] [blame] | 54 | void amd_initenv(void) |
| 55 | { |
| 56 | AMD_INTERFACE_PARAMS AmdParamStruct; |
| 57 | PCI_ADDR PciAddress; |
| 58 | UINT32 PciValue; |
| 59 | |
| 60 | /* Initialize Subordinate Bus Number and Secondary Bus Number |
| 61 | * In platform BIOS this address is allocated by PCI enumeration code |
| 62 | Modify D1F0x18 |
| 63 | */ |
| 64 | PciAddress.Address.Bus = 0; |
| 65 | PciAddress.Address.Device = 1; |
| 66 | PciAddress.Address.Function = 0; |
| 67 | PciAddress.Address.Register = 0x18; |
| 68 | /* Write to D1F0x18 */ |
| 69 | LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); |
| 70 | PciValue |= 0x00010100; |
| 71 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); |
| 72 | |
| 73 | /* Initialize GMM Base Address for Legacy Bridge Mode |
| 74 | * Modify B1D5F0x18 |
| 75 | */ |
| 76 | PciAddress.Address.Bus = 1; |
| 77 | PciAddress.Address.Device = 5; |
| 78 | PciAddress.Address.Function = 0; |
| 79 | PciAddress.Address.Register = 0x18; |
| 80 | |
| 81 | LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); |
| 82 | PciValue |= 0x96000000; |
| 83 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); |
| 84 | |
| 85 | /* Initialize FB Base Address for Legacy Bridge Mode |
| 86 | * Modify B1D5F0x10 |
| 87 | */ |
| 88 | PciAddress.Address.Register = 0x10; |
| 89 | LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); |
| 90 | PciValue |= 0x80000000; |
| 91 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); |
| 92 | |
Elyes HAOUAS | 79ccc69 | 2020-02-24 13:43:39 +0100 | [diff] [blame] | 93 | /* Initialize GMM Base Address for PCIe Mode |
Kyösti Mälkki | 4a08e15 | 2014-12-14 19:41:54 +0200 | [diff] [blame] | 94 | * Modify B0D1F0x18 |
| 95 | */ |
| 96 | PciAddress.Address.Bus = 0; |
| 97 | PciAddress.Address.Device = 1; |
| 98 | PciAddress.Address.Function = 0; |
| 99 | PciAddress.Address.Register = 0x18; |
| 100 | |
| 101 | LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); |
| 102 | PciValue |= 0x96000000; |
| 103 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); |
| 104 | |
Elyes HAOUAS | 79ccc69 | 2020-02-24 13:43:39 +0100 | [diff] [blame] | 105 | /* Initialize FB Base Address for PCIe Mode |
Kyösti Mälkki | 4a08e15 | 2014-12-14 19:41:54 +0200 | [diff] [blame] | 106 | * Modify B0D1F0x10 |
| 107 | */ |
| 108 | PciAddress.Address.Register = 0x10; |
| 109 | LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); |
| 110 | PciValue |= 0x80000000; |
| 111 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); |
| 112 | |
| 113 | /* Initialize MMIO Base and Limit Address |
| 114 | * Modify B0D1F0x20 |
| 115 | */ |
| 116 | PciAddress.Address.Bus = 0; |
| 117 | PciAddress.Address.Device = 1; |
| 118 | PciAddress.Address.Function = 0; |
| 119 | PciAddress.Address.Register = 0x20; |
| 120 | |
| 121 | LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); |
| 122 | PciValue |= 0x96009600; |
| 123 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); |
| 124 | |
| 125 | /* Initialize MMIO Prefetchable Memory Limit and Base |
| 126 | * Modify B0D1F0x24 |
| 127 | */ |
| 128 | PciAddress.Address.Register = 0x24; |
| 129 | LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); |
| 130 | PciValue |= 0x8FF18001; |
| 131 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); |
| 132 | } |