Kyösti Mälkki | 48518f0 | 2014-11-25 14:20:57 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Kyösti Mälkki | 48518f0 | 2014-11-25 14:20:57 +0200 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <cpu/x86/mtrr.h> |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 17 | #include <cpu/amd/msr.h> |
Elyes HAOUAS | 8a64370 | 2018-10-23 17:10:27 +0200 | [diff] [blame] | 18 | #include <cpu/amd/mtrr.h> |
Kyösti Mälkki | d610c58 | 2017-03-05 06:28:18 +0200 | [diff] [blame] | 19 | #include <northbridge/amd/agesa/agesa_helper.h> |
| 20 | #include <AGESA.h> |
Elyes HAOUAS | 19f5ba8 | 2018-10-14 14:52:06 +0200 | [diff] [blame^] | 21 | #include <amdlib.h> |
Kyösti Mälkki | 48518f0 | 2014-11-25 14:20:57 +0200 | [diff] [blame] | 22 | |
| 23 | /* Define AMD Ontario APPU SSID/SVID */ |
| 24 | #define AMD_APU_SVID 0x1022 |
| 25 | #define AMD_APU_SSID 0x1234 |
| 26 | |
| 27 | void amd_initcpuio(void) |
| 28 | { |
| 29 | UINT64 MsrReg; |
| 30 | UINT32 PciData; |
| 31 | PCI_ADDR PciAddress; |
| 32 | AMD_CONFIG_PARAMS StdHeader; |
| 33 | |
| 34 | /* Enable legacy video routing: D18F1xF4 VGA Enable */ |
| 35 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4); |
| 36 | PciData = 1; |
| 37 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 38 | |
| 39 | /* The platform BIOS needs to ensure the memory ranges of SB800 legacy |
| 40 | * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are |
| 41 | * set to non-posted regions. |
| 42 | */ |
| 43 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); |
| 44 | PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000 |
| 45 | PciData |= 1 << 7; // set NP (non-posted) bit |
| 46 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 47 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); |
| 48 | PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000 |
| 49 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 50 | |
| 51 | /* Map the remaining PCI hole as posted MMIO */ |
| 52 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); |
| 53 | PciData = 0x00FECF00; // last address before non-posted range |
| 54 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
Elyes HAOUAS | 8a64370 | 2018-10-23 17:10:27 +0200 | [diff] [blame] | 55 | LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader); |
Kyösti Mälkki | 48518f0 | 2014-11-25 14:20:57 +0200 | [diff] [blame] | 56 | MsrReg = (MsrReg >> 8) | 3; |
| 57 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); |
| 58 | PciData = (UINT32) MsrReg; |
| 59 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 60 | |
| 61 | /* Send all IO (0000-FFFF) to southbridge. */ |
| 62 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4); |
| 63 | PciData = 0x0000F000; |
| 64 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 65 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0); |
| 66 | PciData = 0x00000003; |
| 67 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 68 | } |
| 69 | |
| 70 | void amd_initmmio(void) |
| 71 | { |
| 72 | UINT64 MsrReg; |
| 73 | UINT32 PciData; |
| 74 | PCI_ADDR PciAddress; |
| 75 | AMD_CONFIG_PARAMS StdHeader; |
| 76 | |
| 77 | /* |
| 78 | Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base |
| 79 | Address MSR register. |
| 80 | */ |
| 81 | MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 82 | LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader); |
Kyösti Mälkki | 48518f0 | 2014-11-25 14:20:57 +0200 | [diff] [blame] | 83 | |
Kyösti Mälkki | 48518f0 | 2014-11-25 14:20:57 +0200 | [diff] [blame] | 84 | /* Set Ontario Link Data */ |
| 85 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE0); |
| 86 | PciData = 0x01308002; |
| 87 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 88 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE4); |
| 89 | PciData = (AMD_APU_SSID << 0x10) | AMD_APU_SVID; |
| 90 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
Kyösti Mälkki | 036a581 | 2016-11-20 07:45:17 +0200 | [diff] [blame] | 91 | |
| 92 | /* Set ROM cache onto WP to decrease post time */ |
| 93 | MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | MTRR_TYPE_WRPROT; |
Elyes HAOUAS | d50cf23 | 2018-10-17 20:18:17 +0200 | [diff] [blame] | 94 | LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); |
Kyösti Mälkki | 036a581 | 2016-11-20 07:45:17 +0200 | [diff] [blame] | 95 | MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | MTRR_PHYS_MASK_VALID; |
Elyes HAOUAS | d50cf23 | 2018-10-17 20:18:17 +0200 | [diff] [blame] | 96 | LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); |
Kyösti Mälkki | 7d25651 | 2016-11-20 08:03:49 +0200 | [diff] [blame] | 97 | |
| 98 | /* Set P-state 0 (1600 MHz) early to save a few ms of boot time */ |
| 99 | MsrReg = 0; |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 100 | LibAmdMsrWrite(PS_CTL_REG, &MsrReg, &StdHeader); |
Kyösti Mälkki | 48518f0 | 2014-11-25 14:20:57 +0200 | [diff] [blame] | 101 | } |
Kyösti Mälkki | 4a08e15 | 2014-12-14 19:41:54 +0200 | [diff] [blame] | 102 | |
| 103 | void amd_initenv(void) |
| 104 | { |
| 105 | AMD_INTERFACE_PARAMS AmdParamStruct; |
| 106 | PCI_ADDR PciAddress; |
| 107 | UINT32 PciValue; |
| 108 | |
| 109 | /* Initialize Subordinate Bus Number and Secondary Bus Number |
| 110 | * In platform BIOS this address is allocated by PCI enumeration code |
| 111 | Modify D1F0x18 |
| 112 | */ |
| 113 | PciAddress.Address.Bus = 0; |
| 114 | PciAddress.Address.Device = 1; |
| 115 | PciAddress.Address.Function = 0; |
| 116 | PciAddress.Address.Register = 0x18; |
| 117 | /* Write to D1F0x18 */ |
| 118 | LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); |
| 119 | PciValue |= 0x00010100; |
| 120 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); |
| 121 | |
| 122 | /* Initialize GMM Base Address for Legacy Bridge Mode |
| 123 | * Modify B1D5F0x18 |
| 124 | */ |
| 125 | PciAddress.Address.Bus = 1; |
| 126 | PciAddress.Address.Device = 5; |
| 127 | PciAddress.Address.Function = 0; |
| 128 | PciAddress.Address.Register = 0x18; |
| 129 | |
| 130 | LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); |
| 131 | PciValue |= 0x96000000; |
| 132 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); |
| 133 | |
| 134 | /* Initialize FB Base Address for Legacy Bridge Mode |
| 135 | * Modify B1D5F0x10 |
| 136 | */ |
| 137 | PciAddress.Address.Register = 0x10; |
| 138 | LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); |
| 139 | PciValue |= 0x80000000; |
| 140 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); |
| 141 | |
| 142 | /* Initialize GMM Base Address for Pcie Mode |
| 143 | * Modify B0D1F0x18 |
| 144 | */ |
| 145 | PciAddress.Address.Bus = 0; |
| 146 | PciAddress.Address.Device = 1; |
| 147 | PciAddress.Address.Function = 0; |
| 148 | PciAddress.Address.Register = 0x18; |
| 149 | |
| 150 | LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); |
| 151 | PciValue |= 0x96000000; |
| 152 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); |
| 153 | |
| 154 | /* Initialize FB Base Address for Pcie Mode |
| 155 | * Modify B0D1F0x10 |
| 156 | */ |
| 157 | PciAddress.Address.Register = 0x10; |
| 158 | LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); |
| 159 | PciValue |= 0x80000000; |
| 160 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); |
| 161 | |
| 162 | /* Initialize MMIO Base and Limit Address |
| 163 | * Modify B0D1F0x20 |
| 164 | */ |
| 165 | PciAddress.Address.Bus = 0; |
| 166 | PciAddress.Address.Device = 1; |
| 167 | PciAddress.Address.Function = 0; |
| 168 | PciAddress.Address.Register = 0x20; |
| 169 | |
| 170 | LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); |
| 171 | PciValue |= 0x96009600; |
| 172 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); |
| 173 | |
| 174 | /* Initialize MMIO Prefetchable Memory Limit and Base |
| 175 | * Modify B0D1F0x24 |
| 176 | */ |
| 177 | PciAddress.Address.Register = 0x24; |
| 178 | LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); |
| 179 | PciValue |= 0x8FF18001; |
| 180 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); |
| 181 | } |