commit 79ccc6933284ca02d17d9e1eda9a531ce43e1f65
author Elyes HAOUAS <ehaouas@noos.fr> Mon Feb 24 13:43:39 2020 +0100
committer Patrick Georgi <pgeorgi@google.com> Wed Mar 04 15:43:30 2020 +0000
tree 49fe1b78916338575b1a6bec931e2fb885cc311a
parent f3161df2eba8d61445372a9c732c61a1947064bd

src: capitalize 'PCIe'

Change-Id: I55bbb535372dc9af556b95ba162f02ffead2b9e2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/cpu/amd/agesa/family14/fixme.c

diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c
index be7c635..658434d 100644
--- a/src/cpu/amd/agesa/family14/fixme.c
+++ b/src/cpu/amd/agesa/family14/fixme.c
@@ -100,7 +100,7 @@
 	PciValue |= 0x80000000;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 
-	/* Initialize GMM Base Address for Pcie Mode
+	/* Initialize GMM Base Address for PCIe Mode
 	 *      Modify B0D1F0x18
 	 */
 	PciAddress.Address.Bus = 0;
@@ -112,7 +112,7 @@
 	PciValue |= 0x96000000;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 
-	/* Initialize FB Base Address for Pcie Mode
+	/* Initialize FB Base Address for PCIe Mode
 	 *      Modify B0D1F0x10
 	 */
 	PciAddress.Address.Register = 0x10;