Kyösti Mälkki | 48518f0 | 2014-11-25 14:20:57 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <cpu/x86/mtrr.h> |
| 21 | #include <northbridge/amd/agesa/agesawrapper.h> |
| 22 | #include "amdlib.h" |
| 23 | |
| 24 | /* Define AMD Ontario APPU SSID/SVID */ |
| 25 | #define AMD_APU_SVID 0x1022 |
| 26 | #define AMD_APU_SSID 0x1234 |
| 27 | |
| 28 | void amd_initcpuio(void) |
| 29 | { |
| 30 | UINT64 MsrReg; |
| 31 | UINT32 PciData; |
| 32 | PCI_ADDR PciAddress; |
| 33 | AMD_CONFIG_PARAMS StdHeader; |
| 34 | |
| 35 | /* Enable legacy video routing: D18F1xF4 VGA Enable */ |
| 36 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4); |
| 37 | PciData = 1; |
| 38 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 39 | |
| 40 | /* The platform BIOS needs to ensure the memory ranges of SB800 legacy |
| 41 | * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are |
| 42 | * set to non-posted regions. |
| 43 | */ |
| 44 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); |
| 45 | PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000 |
| 46 | PciData |= 1 << 7; // set NP (non-posted) bit |
| 47 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 48 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); |
| 49 | PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000 |
| 50 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 51 | |
| 52 | /* Map the remaining PCI hole as posted MMIO */ |
| 53 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); |
| 54 | PciData = 0x00FECF00; // last address before non-posted range |
| 55 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 56 | LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader); |
| 57 | MsrReg = (MsrReg >> 8) | 3; |
| 58 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); |
| 59 | PciData = (UINT32) MsrReg; |
| 60 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 61 | |
| 62 | /* Send all IO (0000-FFFF) to southbridge. */ |
| 63 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4); |
| 64 | PciData = 0x0000F000; |
| 65 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 66 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0); |
| 67 | PciData = 0x00000003; |
| 68 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 69 | } |
| 70 | |
| 71 | void amd_initmmio(void) |
| 72 | { |
| 73 | UINT64 MsrReg; |
| 74 | UINT32 PciData; |
| 75 | PCI_ADDR PciAddress; |
| 76 | AMD_CONFIG_PARAMS StdHeader; |
| 77 | |
| 78 | /* |
| 79 | Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base |
| 80 | Address MSR register. |
| 81 | */ |
| 82 | MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; |
| 83 | LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); |
| 84 | |
| 85 | /* |
| 86 | Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. |
| 87 | */ |
| 88 | LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader); |
| 89 | MsrReg = MsrReg | 0x0000400000000000ull; |
| 90 | LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader); |
| 91 | |
| 92 | /* Set Ontario Link Data */ |
| 93 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE0); |
| 94 | PciData = 0x01308002; |
| 95 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 96 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE4); |
| 97 | PciData = (AMD_APU_SSID << 0x10) | AMD_APU_SVID; |
| 98 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 99 | } |