Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 2 | |
Arthur Heymans | bab9e2e | 2021-05-29 07:30:33 +0200 | [diff] [blame] | 3 | #include <acpi/acpi.h> |
Kyösti Mälkki | 021c621 | 2021-01-26 11:28:47 +0200 | [diff] [blame] | 4 | #include <amdblocks/acpi.h> |
Arthur Heymans | bab9e2e | 2021-05-29 07:30:33 +0200 | [diff] [blame] | 5 | #include <amdblocks/agesawrapper.h> |
| 6 | #include <amdblocks/agesawrapper_call.h> |
Michał Żygowski | 5a66202 | 2019-12-02 17:02:00 +0100 | [diff] [blame] | 7 | #include <amdblocks/biosram.h> |
Arthur Heymans | bab9e2e | 2021-05-29 07:30:33 +0200 | [diff] [blame] | 8 | #include <amdblocks/psp.h> |
Marshall Dawson | 18b477e | 2017-09-21 12:27:12 -0600 | [diff] [blame] | 9 | #include <arch/cpu.h> |
Kyösti Mälkki | a963acd | 2019-08-16 20:34:25 +0300 | [diff] [blame] | 10 | #include <arch/romstage.h> |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 11 | #include <cbmem.h> |
Marshall Dawson | 18b477e | 2017-09-21 12:27:12 -0600 | [diff] [blame] | 12 | #include <commonlib/helpers.h> |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 13 | #include <console/console.h> |
Arthur Heymans | bab9e2e | 2021-05-29 07:30:33 +0200 | [diff] [blame] | 14 | #include <cpu/amd/mtrr.h> |
| 15 | #include <cpu/x86/msr.h> |
| 16 | #include <cpu/x86/mtrr.h> |
| 17 | #include <cpu/x86/smm.h> |
Marshall Dawson | 3e4e4c5 | 2017-11-10 16:08:37 -0700 | [diff] [blame] | 18 | #include <device/device.h> |
Arthur Heymans | bab9e2e | 2021-05-29 07:30:33 +0200 | [diff] [blame] | 19 | #include <device/pci_ops.h> |
Daniel Kurtz | c6c8972 | 2018-05-24 17:57:37 -0600 | [diff] [blame] | 20 | #include <elog.h> |
Arthur Heymans | bab9e2e | 2021-05-29 07:30:33 +0200 | [diff] [blame] | 21 | #include <program_loading.h> |
| 22 | #include <romstage_common.h> |
| 23 | #include <romstage_handoff.h> |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 24 | #include <soc/northbridge.h> |
Felix Held | dba3229 | 2020-03-31 23:54:44 +0200 | [diff] [blame] | 25 | #include <soc/pci_devs.h> |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 26 | #include <soc/southbridge.h> |
Arthur Heymans | 796147f | 2022-02-15 10:59:41 +0100 | [diff] [blame] | 27 | #include <stdint.h> |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 28 | |
Elyes HAOUAS | c338507 | 2019-03-21 15:38:06 +0100 | [diff] [blame] | 29 | #include "chip.h" |
| 30 | |
Kyösti Mälkki | 9e591c4 | 2021-01-09 12:37:25 +0200 | [diff] [blame] | 31 | void __weak mainboard_romstage_entry(void) |
Martin Roth | 2c3e3ef | 2018-04-11 16:35:08 -0600 | [diff] [blame] | 32 | { |
| 33 | /* By default, don't do anything */ |
| 34 | } |
| 35 | |
Raul E Rangel | 873b4e7 | 2018-06-12 10:53:55 -0600 | [diff] [blame] | 36 | static void agesa_call(void) |
| 37 | { |
| 38 | post_code(0x37); |
Kyösti Mälkki | 6e512c4 | 2018-06-14 06:57:05 +0300 | [diff] [blame] | 39 | do_agesawrapper(AMD_INIT_RESET, "amdinitreset"); |
Raul E Rangel | 873b4e7 | 2018-06-12 10:53:55 -0600 | [diff] [blame] | 40 | |
| 41 | post_code(0x38); |
| 42 | /* APs will not exit amdinitearly */ |
Kyösti Mälkki | 6e512c4 | 2018-06-14 06:57:05 +0300 | [diff] [blame] | 43 | do_agesawrapper(AMD_INIT_EARLY, "amdinitearly"); |
Raul E Rangel | 873b4e7 | 2018-06-12 10:53:55 -0600 | [diff] [blame] | 44 | } |
| 45 | |
| 46 | static void bsp_agesa_call(void) |
| 47 | { |
| 48 | set_ap_entry_ptr(agesa_call); /* indicate the path to the AP */ |
| 49 | agesa_call(); |
| 50 | } |
Arthur Heymans | bab9e2e | 2021-05-29 07:30:33 +0200 | [diff] [blame] | 51 | void __noreturn romstage_main(void) |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 52 | { |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 53 | msr_t base, mask; |
| 54 | msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); |
| 55 | int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT; |
Kyösti Mälkki | 9e591c4 | 2021-01-09 12:37:25 +0200 | [diff] [blame] | 56 | int s3_resume = acpi_is_wakeup_s3(); |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 57 | int i; |
| 58 | |
Felix Held | dba3229 | 2020-03-31 23:54:44 +0200 | [diff] [blame] | 59 | soc_enable_psp_early(); |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 60 | if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) |
Felix Held | dba3229 | 2020-03-31 23:54:44 +0200 | [diff] [blame] | 61 | psp_load_named_blob(BLOB_SMU_FW, "smu_fw"); |
Raul E Rangel | 873b4e7 | 2018-06-12 10:53:55 -0600 | [diff] [blame] | 62 | |
Kyösti Mälkki | 9e591c4 | 2021-01-09 12:37:25 +0200 | [diff] [blame] | 63 | mainboard_romstage_entry(); |
Kyösti Mälkki | 7f50afb | 2019-09-11 17:12:26 +0300 | [diff] [blame] | 64 | elog_boot_notify(s3_resume); |
Raul E Rangel | 873b4e7 | 2018-06-12 10:53:55 -0600 | [diff] [blame] | 65 | |
| 66 | bsp_agesa_call(); |
| 67 | |
Marshall Dawson | 8f2a7e0 | 2017-11-01 11:44:48 -0600 | [diff] [blame] | 68 | if (!s3_resume) { |
| 69 | post_code(0x40); |
Kyösti Mälkki | 6e512c4 | 2018-06-14 06:57:05 +0300 | [diff] [blame] | 70 | do_agesawrapper(AMD_INIT_POST, "amdinitpost"); |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 71 | |
Marshall Dawson | 8f2a7e0 | 2017-11-01 11:44:48 -0600 | [diff] [blame] | 72 | post_code(0x41); |
| 73 | /* |
| 74 | * TODO: This is a hack to work around current AGESA behavior. |
| 75 | * AGESA needs to change to reflect that coreboot owns |
| 76 | * the MTRRs. |
| 77 | * |
| 78 | * After setting up DRAM, AGESA also completes the configuration |
| 79 | * of the MTRRs, setting regions to WB. Anything written to |
Elyes HAOUAS | ba4dbf8 | 2021-01-16 15:02:17 +0100 | [diff] [blame] | 80 | * memory between now and when CAR is dismantled will be |
Marshall Dawson | 8f2a7e0 | 2017-11-01 11:44:48 -0600 | [diff] [blame] | 81 | * in cache and lost. For now, set the regions UC to ensure |
| 82 | * the writes get to DRAM. |
| 83 | */ |
| 84 | for (i = 0 ; i < vmtrrs ; i++) { |
| 85 | base = rdmsr(MTRR_PHYS_BASE(i)); |
| 86 | mask = rdmsr(MTRR_PHYS_MASK(i)); |
| 87 | if (!(mask.lo & MTRR_PHYS_MASK_VALID)) |
| 88 | continue; |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 89 | |
Marshall Dawson | 8f2a7e0 | 2017-11-01 11:44:48 -0600 | [diff] [blame] | 90 | if ((base.lo & 0x7) == MTRR_TYPE_WRBACK) { |
| 91 | base.lo &= ~0x7; |
| 92 | base.lo |= MTRR_TYPE_UNCACHEABLE; |
| 93 | wrmsr(MTRR_PHYS_BASE(i), base); |
| 94 | } |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 95 | } |
Marshall Dawson | 8f2a7e0 | 2017-11-01 11:44:48 -0600 | [diff] [blame] | 96 | /* Disable WB from to region 4GB-TOM2. */ |
| 97 | msr_t sys_cfg = rdmsr(SYSCFG_MSR); |
| 98 | sys_cfg.lo &= ~SYSCFG_MSR_TOM2WB; |
| 99 | wrmsr(SYSCFG_MSR, sys_cfg); |
| 100 | } else { |
| 101 | printk(BIOS_INFO, "S3 detected\n"); |
| 102 | post_code(0x60); |
Kyösti Mälkki | 6e512c4 | 2018-06-14 06:57:05 +0300 | [diff] [blame] | 103 | do_agesawrapper(AMD_INIT_RESUME, "amdinitresume"); |
Marshall Dawson | 8f2a7e0 | 2017-11-01 11:44:48 -0600 | [diff] [blame] | 104 | |
| 105 | post_code(0x61); |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 106 | } |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 107 | |
| 108 | post_code(0x42); |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 109 | psp_notify_dram(); |
| 110 | |
| 111 | post_code(0x43); |
Marshall Dawson | 8f2a7e0 | 2017-11-01 11:44:48 -0600 | [diff] [blame] | 112 | if (cbmem_recovery(s3_resume)) |
| 113 | printk(BIOS_CRIT, "Failed to recover cbmem\n"); |
| 114 | if (romstage_handoff_init(s3_resume)) |
| 115 | printk(BIOS_ERR, "Failed to set romstage handoff data\n"); |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 116 | |
Kyösti Mälkki | 7cdb047 | 2019-08-08 11:16:06 +0300 | [diff] [blame] | 117 | if (CONFIG(SMM_TSEG)) |
| 118 | smm_list_regions(); |
| 119 | |
Marshall Dawson | 18b477e | 2017-09-21 12:27:12 -0600 | [diff] [blame] | 120 | post_code(0x44); |
Arthur Heymans | 876a1b4 | 2022-02-15 11:06:10 +0100 | [diff] [blame] | 121 | prepare_and_run_postcar(); |
Arthur Heymans | bab9e2e | 2021-05-29 07:30:33 +0200 | [diff] [blame] | 122 | die("failed to load postcar\n"); |
Arthur Heymans | 796147f | 2022-02-15 10:59:41 +0100 | [diff] [blame] | 123 | } |
Marshall Dawson | 18b477e | 2017-09-21 12:27:12 -0600 | [diff] [blame] | 124 | |
Arthur Heymans | 796147f | 2022-02-15 10:59:41 +0100 | [diff] [blame] | 125 | void fill_postcar_frame(struct postcar_frame *pcf) |
| 126 | { |
| 127 | uintptr_t top_of_ram = (uintptr_t)cbmem_top(); |
| 128 | postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 129 | |
Subrata Banik | 3eff037 | 2019-09-10 15:51:17 +0530 | [diff] [blame] | 130 | /* Cache the TSEG region */ |
Arthur Heymans | 796147f | 2022-02-15 10:59:41 +0100 | [diff] [blame] | 131 | postcar_enable_tseg_cache(pcf); |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 132 | } |
Richard Spiegel | 67c2a7b | 2017-11-09 16:04:35 -0700 | [diff] [blame] | 133 | |
| 134 | void SetMemParams(AMD_POST_PARAMS *PostParams) |
| 135 | { |
| 136 | const struct soc_amd_stoneyridge_config *cfg; |
Kyösti Mälkki | e737755 | 2018-06-21 16:20:55 +0300 | [diff] [blame] | 137 | const struct device *dev = pcidev_path_on_root(GNB_DEVFN); |
Richard Spiegel | 67c2a7b | 2017-11-09 16:04:35 -0700 | [diff] [blame] | 138 | |
| 139 | if (!dev || !dev->chip_info) { |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 140 | printk(BIOS_ERR, "Cannot find SoC devicetree config\n"); |
Aaron Durbin | 36dbf1d | 2017-11-10 13:16:23 -0700 | [diff] [blame] | 141 | /* In case of a BIOS error, only attempt to set UMA. */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 142 | PostParams->MemConfig.UmaMode = CONFIG(GFXUMA) ? |
Aaron Durbin | 36dbf1d | 2017-11-10 13:16:23 -0700 | [diff] [blame] | 143 | UMA_AUTO : UMA_NONE; |
Richard Spiegel | 67c2a7b | 2017-11-09 16:04:35 -0700 | [diff] [blame] | 144 | return; |
| 145 | } |
| 146 | |
| 147 | cfg = dev->chip_info; |
Aaron Durbin | 36dbf1d | 2017-11-10 13:16:23 -0700 | [diff] [blame] | 148 | |
Richard Spiegel | 67c2a7b | 2017-11-09 16:04:35 -0700 | [diff] [blame] | 149 | PostParams->MemConfig.EnableMemClr = cfg->dram_clear_on_reset; |
Aaron Durbin | 36dbf1d | 2017-11-10 13:16:23 -0700 | [diff] [blame] | 150 | |
| 151 | switch (cfg->uma_mode) { |
| 152 | case UMAMODE_NONE: |
| 153 | PostParams->MemConfig.UmaMode = UMA_NONE; |
| 154 | break; |
| 155 | case UMAMODE_SPECIFIED_SIZE: |
| 156 | PostParams->MemConfig.UmaMode = UMA_SPECIFIED; |
| 157 | /* 64 KiB blocks. */ |
| 158 | PostParams->MemConfig.UmaSize = cfg->uma_size / (64 * KiB); |
| 159 | break; |
| 160 | case UMAMODE_AUTO_LEGACY: |
| 161 | PostParams->MemConfig.UmaMode = UMA_AUTO; |
| 162 | PostParams->MemConfig.UmaVersion = UMA_LEGACY; |
| 163 | break; |
| 164 | case UMAMODE_AUTO_NON_LEGACY: |
| 165 | PostParams->MemConfig.UmaMode = UMA_AUTO; |
| 166 | PostParams->MemConfig.UmaVersion = UMA_NON_LEGACY; |
| 167 | break; |
| 168 | } |
Richard Spiegel | 67c2a7b | 2017-11-09 16:04:35 -0700 | [diff] [blame] | 169 | } |
Richard Spiegel | dd9b1d1 | 2018-09-20 14:50:11 -0700 | [diff] [blame] | 170 | |
| 171 | void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly) |
| 172 | { |
| 173 | const struct soc_amd_stoneyridge_config *cfg; |
Kyösti Mälkki | e737755 | 2018-06-21 16:20:55 +0300 | [diff] [blame] | 174 | const struct device *dev = pcidev_path_on_root(GNB_DEVFN); |
Richard Spiegel | dd9b1d1 | 2018-09-20 14:50:11 -0700 | [diff] [blame] | 175 | struct _PLATFORM_CONFIGURATION *platform; |
| 176 | |
| 177 | if (!dev || !dev->chip_info) { |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 178 | printk(BIOS_WARNING, "Cannot find SoC devicetree" |
Richard Spiegel | dd9b1d1 | 2018-09-20 14:50:11 -0700 | [diff] [blame] | 179 | " config, STAPM unchanged\n"); |
| 180 | return; |
| 181 | } |
| 182 | cfg = dev->chip_info; |
| 183 | platform = &InitEarly->PlatformConfig; |
Richard Spiegel | de5d040 | 2018-10-11 08:15:43 -0700 | [diff] [blame] | 184 | if ((cfg->stapm_percent) && (cfg->stapm_time_ms) && |
| 185 | (cfg->stapm_power_mw)) { |
Richard Spiegel | dd9b1d1 | 2018-09-20 14:50:11 -0700 | [diff] [blame] | 186 | platform->PlatStapmConfig.CfgStapmScalar = cfg->stapm_percent; |
| 187 | platform->PlatStapmConfig.CfgStapmTimeConstant = |
Richard Spiegel | de5d040 | 2018-10-11 08:15:43 -0700 | [diff] [blame] | 188 | cfg->stapm_time_ms; |
| 189 | platform->PkgPwrLimitDC = cfg->stapm_power_mw; |
| 190 | platform->PkgPwrLimitAC = cfg->stapm_power_mw; |
Richard Spiegel | dd9b1d1 | 2018-09-20 14:50:11 -0700 | [diff] [blame] | 191 | platform->PlatStapmConfig.CfgStapmBoost = StapmBoostEnabled; |
| 192 | } |
| 193 | } |
Kyösti Mälkki | 021c621 | 2021-01-26 11:28:47 +0200 | [diff] [blame] | 194 | |
| 195 | static void migrate_power_state(int is_recovery) |
| 196 | { |
| 197 | struct chipset_power_state *state; |
| 198 | state = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*state)); |
| 199 | if (state) { |
| 200 | acpi_fill_pm_gpe_state(&state->gpe_state); |
| 201 | acpi_pm_gpe_add_events_print_events(); |
| 202 | } |
Kyösti Mälkki | 021c621 | 2021-01-26 11:28:47 +0200 | [diff] [blame] | 203 | } |
Kyösti Mälkki | fa3bc04 | 2022-03-31 07:40:10 +0300 | [diff] [blame] | 204 | CBMEM_CREATION_HOOK(migrate_power_state); |