Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Martin Roth | 5474eb1 | 2018-05-26 19:22:33 -0600 | [diff] [blame] | 2 | |
Kyösti Mälkki | de64078 | 2019-12-03 07:30:26 +0200 | [diff] [blame] | 3 | #include <arch/bootblock.h> |
Angel Pons | b274ec7 | 2021-01-20 14:03:44 +0100 | [diff] [blame] | 4 | #include <assert.h> |
Angel Pons | 37cae54 | 2021-02-02 16:28:07 +0100 | [diff] [blame] | 5 | #include <device/pci_ops.h> |
Angel Pons | b274ec7 | 2021-01-20 14:03:44 +0100 | [diff] [blame] | 6 | #include <types.h> |
Elyes HAOUAS | 77d3b65 | 2021-01-31 08:28:45 +0100 | [diff] [blame] | 7 | |
Angel Pons | 3ab19b3 | 2020-07-22 16:29:54 +0200 | [diff] [blame] | 8 | #include "ironlake.h" |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 9 | |
Angel Pons | b274ec7 | 2021-01-20 14:03:44 +0100 | [diff] [blame] | 10 | static uint32_t encode_pciexbar_length(void) |
| 11 | { |
| 12 | /* NOTE: Ironlake uses a different encoding for the PCIEXBAR length field */ |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 13 | switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) { |
Angel Pons | b274ec7 | 2021-01-20 14:03:44 +0100 | [diff] [blame] | 14 | case 256: return 0 << 1; |
| 15 | case 128: return 6 << 1; |
| 16 | case 64: return 7 << 1; |
| 17 | default: return dead_code_t(uint32_t); |
| 18 | } |
| 19 | } |
| 20 | |
Arthur Heymans | 2882253 | 2019-10-10 15:50:04 +0200 | [diff] [blame] | 21 | void bootblock_early_northbridge_init(void) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 22 | { |
Angel Pons | b274ec7 | 2021-01-20 14:03:44 +0100 | [diff] [blame] | 23 | /* |
| 24 | * The QuickPath bus number is the topmost bus number, as per the value |
Martin Roth | 50863da | 2021-10-01 14:37:30 -0600 | [diff] [blame] | 25 | * of the SAD_PCIEXBAR register. The register defaults to 256 buses on |
Angel Pons | b274ec7 | 2021-01-20 14:03:44 +0100 | [diff] [blame] | 26 | * reset. Thus, hardcode the bus number when first setting up PCIEXBAR. |
| 27 | */ |
| 28 | const pci_devfn_t qpi_sad = PCI_DEV(255, 0, 1); |
| 29 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 30 | const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; |
Angel Pons | b274ec7 | 2021-01-20 14:03:44 +0100 | [diff] [blame] | 31 | pci_io_write_config32(qpi_sad, SAD_PCIEXBAR + 4, 0); |
| 32 | pci_io_write_config32(qpi_sad, SAD_PCIEXBAR, reg32); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 33 | } |