nb/intel/ironlake: Use MMCONF_BUS_NUMBER everywhere
Bootblock enabling needs some special handling. Also, the definition of
the `get_pcie_bar` function is incorrect for Ironlake, so remove it.
With this patch, using 64 and 128 for MMCONF_BUS_NUMBER should work.
However, it has not been tested. Using 256 busses should still work.
Change-Id: Ic466ddc7b80f60af5cbff53583281440f02974c7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49761
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/ironlake/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c
index 89eb8133..4b174cb 100644
--- a/src/northbridge/intel/ironlake/bootblock.c
+++ b/src/northbridge/intel/ironlake/bootblock.c
@@ -1,11 +1,32 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/bootblock.h>
+#include <assert.h>
#include <device/pci_ops.h>
+#include <types.h>
#include "ironlake.h"
+static uint32_t encode_pciexbar_length(void)
+{
+ /* NOTE: Ironlake uses a different encoding for the PCIEXBAR length field */
+ switch (CONFIG_MMCONF_BUS_NUMBER) {
+ case 256: return 0 << 1;
+ case 128: return 6 << 1;
+ case 64: return 7 << 1;
+ default: return dead_code_t(uint32_t);
+ }
+}
+
void bootblock_early_northbridge_init(void)
{
- pci_io_write_config32(QPI_SAD, SAD_PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1);
- pci_io_write_config32(QPI_SAD, SAD_PCIEXBAR + 4, 0);
+ /*
+ * The QuickPath bus number is the topmost bus number, as per the value
+ * of the SAD_PCIEXBAR register. The register defaults to 256 busses on
+ * reset. Thus, hardcode the bus number when first setting up PCIEXBAR.
+ */
+ const pci_devfn_t qpi_sad = PCI_DEV(255, 0, 1);
+
+ const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
+ pci_io_write_config32(qpi_sad, SAD_PCIEXBAR + 4, 0);
+ pci_io_write_config32(qpi_sad, SAD_PCIEXBAR, reg32);
}