| commit | 77d3b655ed5aa0bff07cc82fe5f7abc00dacf41b | [log] [tgz] |
|---|---|---|
| author | Elyes HAOUAS <ehaouas@noos.fr> | Sun Jan 31 08:28:45 2021 +0100 |
| committer | Patrick Georgi <pgeorgi@google.com> | Mon Feb 01 09:01:00 2021 +0000 |
| tree | 1493f0c72d702be3bad113b27037de52c6be0da0 | |
| parent | 487c1a24f59c19539b6039c54176e87864ab91b8 [diff] [blame] |
nb/intel/ironlake/bootblock.c: include <arch/pci_io_cfg.h> Change-Id: Ide960d7957e8a95961ec3722ad7478926a84c544 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/northbridge/intel/ironlake/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c index 4b174cb..02b63a6 100644 --- a/src/northbridge/intel/ironlake/bootblock.c +++ b/src/northbridge/intel/ironlake/bootblock.c
@@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/bootblock.h> +#include <arch/pci_io_cfg.h> #include <assert.h> -#include <device/pci_ops.h> #include <types.h> + #include "ironlake.h" static uint32_t encode_pciexbar_length(void)