Rename ECAM-specific MMCONF Kconfigs
Currently, the MMCONF Kconfigs only support the Enhanced Configuration
Access mechanism (ECAM) method for accessing the PCI config address
space. Some platforms have a different way of mapping the PCI config
space to memory. This patch renames the following configs to
make it clear that these configs are ECAM-specific:
- NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT
- MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT
- MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS
- MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER
- MMCONF_LENGTH --> ECAM_MMCONF_LENGTH
Please refer to CB:57861 "Proposed coreboot Changes" for more
details.
BUG=b:181098581
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max
Make sure Jenkins verifies that builds on other boards
Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/northbridge/intel/ironlake/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c
index 241eb43..58f49da 100644
--- a/src/northbridge/intel/ironlake/bootblock.c
+++ b/src/northbridge/intel/ironlake/bootblock.c
@@ -10,7 +10,7 @@
static uint32_t encode_pciexbar_length(void)
{
/* NOTE: Ironlake uses a different encoding for the PCIEXBAR length field */
- switch (CONFIG_MMCONF_BUS_NUMBER) {
+ switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
case 256: return 0 << 1;
case 128: return 6 << 1;
case 64: return 7 << 1;
@@ -27,7 +27,7 @@
*/
const pci_devfn_t qpi_sad = PCI_DEV(255, 0, 1);
- const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
+ const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(qpi_sad, SAD_PCIEXBAR + 4, 0);
pci_io_write_config32(qpi_sad, SAD_PCIEXBAR, reg32);
}