Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <assert.h> |
Jeremy Compostella | 79c09ba | 2023-10-20 14:06:36 -0700 | [diff] [blame] | 4 | #include <bootmode.h> |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 5 | #include <console/console.h> |
Jeremy Compostella | a6a5b25 | 2023-09-07 10:08:35 -0700 | [diff] [blame] | 6 | #include <cpu/intel/common/common.h> |
Subrata Banik | a3ad319 | 2022-09-08 09:38:08 -0700 | [diff] [blame] | 7 | #include <cpu/intel/cpu_ids.h> |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 8 | #include <cpu/x86/msr.h> |
| 9 | #include <device/device.h> |
Jeremy Compostella | 79c09ba | 2023-10-20 14:06:36 -0700 | [diff] [blame] | 10 | #include <device/pci.h> |
zhaojohn | a923a43 | 2022-09-22 20:33:57 -0700 | [diff] [blame] | 11 | #include <drivers/wifi/generic/wifi.h> |
Subrata Banik | 7ae5100 | 2023-11-09 14:42:04 +0530 | [diff] [blame] | 12 | #include <elog.h> |
Subrata Banik | e88bee7 | 2022-06-27 16:51:44 +0530 | [diff] [blame] | 13 | #include <fsp/fsp_debug_event.h> |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 14 | #include <fsp/util.h> |
Pratikkumar Prajapati | 10bd2a2 | 2023-06-05 18:18:16 -0700 | [diff] [blame] | 15 | #include <intelbasecode/ramtop.h> |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 16 | #include <intelblocks/cpulib.h> |
Jeremy Compostella | 79c09ba | 2023-10-20 14:06:36 -0700 | [diff] [blame] | 17 | #include <intelblocks/cse.h> |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 18 | #include <intelblocks/pcie_rp.h> |
Eran Mitrani | 222903e | 2022-12-19 11:27:10 -0800 | [diff] [blame] | 19 | #include <option.h> |
Jeremy Compostella | 79c09ba | 2023-10-20 14:06:36 -0700 | [diff] [blame] | 20 | #include <soc/cpu.h> |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 21 | #include <soc/gpio_soc_defs.h> |
| 22 | #include <soc/iomap.h> |
| 23 | #include <soc/msr.h> |
| 24 | #include <soc/pci_devs.h> |
| 25 | #include <soc/pcie.h> |
| 26 | #include <soc/romstage.h> |
| 27 | #include <soc/soc_chip.h> |
| 28 | #include <soc/soc_info.h> |
| 29 | #include <string.h> |
Jeremy Compostella | 79c09ba | 2023-10-20 14:06:36 -0700 | [diff] [blame] | 30 | #include <ux_locales.h> |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 31 | |
| 32 | #define FSP_CLK_NOTUSED 0xFF |
| 33 | #define FSP_CLK_LAN 0x70 |
| 34 | #define FSP_CLK_FREE_RUNNING 0x80 |
| 35 | |
| 36 | static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, |
| 37 | const struct pcie_rp_config *cfg, size_t cfg_count) |
| 38 | { |
| 39 | size_t i; |
Subrata Banik | 3eac049 | 2022-12-06 13:48:44 +0530 | [diff] [blame] | 40 | static unsigned int clk_req_mapping = 0; |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 41 | |
| 42 | for (i = 0; i < cfg_count; i++) { |
Subrata Banik | c0f4b12 | 2022-12-06 14:03:07 +0530 | [diff] [blame] | 43 | if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) { |
| 44 | m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING; |
| 45 | continue; |
| 46 | } |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 47 | if (!(en_mask & BIT(i))) |
| 48 | continue; |
| 49 | if (cfg[i].flags & PCIE_RP_CLK_SRC_UNUSED) |
| 50 | continue; |
Subrata Banik | 64dd9d0 | 2022-12-06 13:55:01 +0530 | [diff] [blame] | 51 | if (!cfg[i].flags && cfg[i].clk_src == 0 && cfg[i].clk_req == 0) { |
| 52 | printk(BIOS_WARNING, "Missing root port clock structure definition\n"); |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 53 | continue; |
Subrata Banik | 64dd9d0 | 2022-12-06 13:55:01 +0530 | [diff] [blame] | 54 | } |
Subrata Banik | 3eac049 | 2022-12-06 13:48:44 +0530 | [diff] [blame] | 55 | if (clk_req_mapping & (1 << cfg[i].clk_req)) |
| 56 | printk(BIOS_WARNING, "Found overlapped clkreq assignment on clk req %d\n" |
| 57 | , cfg[i].clk_req); |
| 58 | if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED)) { |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 59 | m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req; |
Subrata Banik | 3eac049 | 2022-12-06 13:48:44 +0530 | [diff] [blame] | 60 | clk_req_mapping |= 1 << cfg[i].clk_req; |
| 61 | } |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 62 | m_cfg->PcieClkSrcUsage[cfg[i].clk_src] = i; |
| 63 | } |
| 64 | } |
| 65 | |
| 66 | static void fill_fspm_pcie_rp_params(FSP_M_CONFIG *m_cfg, |
| 67 | const struct soc_intel_meteorlake_config *config) |
| 68 | { |
| 69 | /* Disable all PCIe clock sources by default. And set RP irrelevant clock. */ |
| 70 | unsigned int i; |
| 71 | uint8_t max_clock = get_max_pcie_clock(); |
| 72 | |
| 73 | for (i = 0; i < max_clock; i++) { |
| 74 | if (config->pcie_clk_config_flag[i] & PCIE_CLK_FREE_RUNNING) |
| 75 | m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING; |
| 76 | else if (config->pcie_clk_config_flag[i] & PCIE_CLK_LAN) |
| 77 | m_cfg->PcieClkSrcUsage[i] = FSP_CLK_LAN; |
| 78 | else |
| 79 | m_cfg->PcieClkSrcUsage[i] = FSP_CLK_NOTUSED; |
| 80 | m_cfg->PcieClkSrcClkReq[i] = FSP_CLK_NOTUSED; |
| 81 | } |
| 82 | |
| 83 | /* PCIE ports */ |
Subrata Banik | 3a183bc | 2023-06-20 20:29:29 +0530 | [diff] [blame] | 84 | if (CONFIG(SOC_INTEL_METEORLAKE_U_H)) { |
Subrata Banik | 53d7e70 | 2023-06-02 16:07:25 +0530 | [diff] [blame] | 85 | m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pcie_rp_table()); |
| 86 | m_cfg->PchPcieRpEnableMask = 0; /* Don't care about PCH PCIE RP Mask */ |
| 87 | pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, config->pcie_rp, |
| 88 | get_max_pcie_port()); |
| 89 | } else { |
| 90 | /* |
| 91 | * FIXME: Implement PCIe RP mask for `PchPcieRpEnableMask` and |
| 92 | * perform pcie_rp_init(). |
| 93 | */ |
| 94 | m_cfg->PcieRpEnableMask = 0; /* Don't care about SOC/IOE PCIE RP Mask */ |
| 95 | } |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 96 | } |
| 97 | |
| 98 | static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg, |
| 99 | const struct soc_intel_meteorlake_config *config) |
| 100 | { |
| 101 | unsigned int i; |
| 102 | const struct ddi_port_upds { |
| 103 | uint8_t *ddc; |
| 104 | uint8_t *hpd; |
| 105 | } ddi_port_upds[] = { |
| 106 | [DDI_PORT_A] = {&m_cfg->DdiPortADdc, &m_cfg->DdiPortAHpd}, |
| 107 | [DDI_PORT_B] = {&m_cfg->DdiPortBDdc, &m_cfg->DdiPortBHpd}, |
| 108 | [DDI_PORT_C] = {&m_cfg->DdiPortCDdc, &m_cfg->DdiPortCHpd}, |
| 109 | [DDI_PORT_1] = {&m_cfg->DdiPort1Ddc, &m_cfg->DdiPort1Hpd}, |
| 110 | [DDI_PORT_2] = {&m_cfg->DdiPort2Ddc, &m_cfg->DdiPort2Hpd}, |
| 111 | [DDI_PORT_3] = {&m_cfg->DdiPort3Ddc, &m_cfg->DdiPort3Hpd}, |
| 112 | [DDI_PORT_4] = {&m_cfg->DdiPort4Ddc, &m_cfg->DdiPort4Hpd}, |
| 113 | }; |
| 114 | m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(PCI_DEVFN_IGD); |
| 115 | if (m_cfg->InternalGfx) { |
| 116 | /* IGD is enabled, set IGD stolen size to 64MB. */ |
| 117 | m_cfg->IgdDvmt50PreAlloc = IGD_SM_64MB; |
| 118 | /* DP port config */ |
| 119 | m_cfg->DdiPortAConfig = config->ddi_port_A_config; |
| 120 | m_cfg->DdiPortBConfig = config->ddi_port_B_config; |
| 121 | for (i = 0; i < ARRAY_SIZE(ddi_port_upds); i++) { |
| 122 | *ddi_port_upds[i].ddc = !!(config->ddi_ports_config[i] & |
| 123 | DDI_ENABLE_DDC); |
| 124 | *ddi_port_upds[i].hpd = !!(config->ddi_ports_config[i] & |
| 125 | DDI_ENABLE_HPD); |
| 126 | } |
| 127 | } else { |
| 128 | /* IGD is disabled, skip IGD init in FSP. */ |
| 129 | m_cfg->IgdDvmt50PreAlloc = 0; |
| 130 | /* DP port config */ |
| 131 | m_cfg->DdiPortAConfig = 0; |
| 132 | m_cfg->DdiPortBConfig = 0; |
| 133 | for (i = 0; i < ARRAY_SIZE(ddi_port_upds); i++) { |
| 134 | *ddi_port_upds[i].ddc = 0; |
| 135 | *ddi_port_upds[i].hpd = 0; |
| 136 | } |
| 137 | } |
| 138 | } |
| 139 | |
| 140 | static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg, |
| 141 | const struct soc_intel_meteorlake_config *config) |
| 142 | { |
Bora Guvendik | 9f15dee | 2023-05-15 14:28:44 -0700 | [diff] [blame] | 143 | unsigned int i; |
| 144 | |
Subrata Banik | 289f9a5 | 2023-01-20 21:38:05 +0530 | [diff] [blame] | 145 | m_cfg->SaGv = config->sagv; |
Bora Guvendik | 9f15dee | 2023-05-15 14:28:44 -0700 | [diff] [blame] | 146 | |
Subrata Banik | a193308 | 2023-05-22 14:22:37 +0530 | [diff] [blame] | 147 | if (m_cfg->SaGv) { |
| 148 | /* |
| 149 | * Set SaGv work points after reviewing the power and performance impact |
| 150 | * with SaGv set to 1 (Enabled) and various work points between 0-3 being |
| 151 | * enabled. |
| 152 | */ |
| 153 | if (config->sagv_wp_bitmap) |
| 154 | m_cfg->SaGvWpMask = config->sagv_wp_bitmap; |
| 155 | else |
| 156 | m_cfg->SaGvWpMask = SAGV_POINTS_0_1_2_3; |
Bora Guvendik | 9f15dee | 2023-05-15 14:28:44 -0700 | [diff] [blame] | 157 | |
| 158 | for (i = 0; i < HOB_MAX_SAGV_POINTS; i++) { |
| 159 | m_cfg->SaGvFreq[i] = config->sagv_freq_mhz[i]; |
| 160 | m_cfg->SaGvGear[i] = config->sagv_gear[i]; |
| 161 | } |
Subrata Banik | a193308 | 2023-05-22 14:22:37 +0530 | [diff] [blame] | 162 | } |
| 163 | |
Subrata Banik | 289f9a5 | 2023-01-20 21:38:05 +0530 | [diff] [blame] | 164 | m_cfg->RMT = config->rmt; |
Kilari Raasi | ebb28c5 | 2023-11-07 14:05:14 +0530 | [diff] [blame] | 165 | m_cfg->RMC = 0; |
| 166 | m_cfg->MarginLimitCheck = 0; |
Subrata Banik | 8dd962b | 2023-02-03 13:06:51 +0530 | [diff] [blame] | 167 | /* Enable MRC Fast Boot */ |
| 168 | m_cfg->MrcFastBoot = 1; |
Subrata Banik | 9c58830 | 2023-09-22 12:45:45 +0530 | [diff] [blame] | 169 | m_cfg->LowerBasicMemTestSize = config->lower_basic_mem_test_size; |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 170 | } |
| 171 | |
| 172 | static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg, |
| 173 | const struct soc_intel_meteorlake_config *config) |
| 174 | { |
| 175 | m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; |
| 176 | /* CpuRatio Settings */ |
| 177 | if (config->cpu_ratio_override) |
| 178 | m_cfg->CpuRatio = config->cpu_ratio_override; |
| 179 | else |
| 180 | /* Set CpuRatio to match existing MSR value */ |
| 181 | m_cfg->CpuRatio = (rdmsr(MSR_FLEX_RATIO).lo >> 8) & 0xff; |
| 182 | |
| 183 | m_cfg->PrmrrSize = get_valid_prmrr_size(); |
Eran Mitrani | 222903e | 2022-12-19 11:27:10 -0800 | [diff] [blame] | 184 | m_cfg->HyperThreading = get_uint_option("hyper_threading", CONFIG(FSP_HYPERTHREADING)); |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 185 | } |
| 186 | |
Pratikkumar Prajapati | 10bd2a2 | 2023-06-05 18:18:16 -0700 | [diff] [blame] | 187 | static void fill_tme_params(FSP_M_CONFIG *m_cfg) |
| 188 | { |
| 189 | m_cfg->TmeEnable = CONFIG(INTEL_TME) && is_tme_supported(); |
| 190 | if (!m_cfg->TmeEnable) |
| 191 | return; |
Subrata Banik | cbbfd68 | 2023-11-14 01:36:09 +0530 | [diff] [blame] | 192 | m_cfg->GenerateNewTmeKey = CONFIG(TME_KEY_REGENERATION_ON_WARM_BOOT) && |
| 193 | CONFIG(SOC_INTEL_COMMON_BASECODE_RAMTOP); |
Pratikkumar Prajapati | 10bd2a2 | 2023-06-05 18:18:16 -0700 | [diff] [blame] | 194 | if (m_cfg->GenerateNewTmeKey) { |
| 195 | uint32_t ram_top = get_ramtop_addr(); |
| 196 | if (!ram_top) { |
| 197 | printk(BIOS_WARNING, "Invalid exclusion range start address. " |
| 198 | "Full memory encryption is enabled.\n"); |
| 199 | return; |
| 200 | } |
| 201 | m_cfg->TmeExcludeBase = (ram_top - 16*MiB); |
| 202 | m_cfg->TmeExcludeSize = 16*MiB; |
| 203 | } |
| 204 | } |
| 205 | |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 206 | static void fill_fspm_security_params(FSP_M_CONFIG *m_cfg, |
| 207 | const struct soc_intel_meteorlake_config *config) |
| 208 | { |
| 209 | /* Disable BIOS Guard */ |
| 210 | m_cfg->BiosGuard = 0; |
Pratikkumar Prajapati | 10bd2a2 | 2023-06-05 18:18:16 -0700 | [diff] [blame] | 211 | fill_tme_params(m_cfg); |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 212 | } |
| 213 | |
| 214 | static void fill_fspm_uart_params(FSP_M_CONFIG *m_cfg, |
| 215 | const struct soc_intel_meteorlake_config *config) |
| 216 | { |
| 217 | if (CONFIG(DRIVERS_UART_8250IO)) |
| 218 | m_cfg->PcdIsaSerialUartBase = ISA_SERIAL_BASE_ADDR_3F8; |
| 219 | m_cfg->SerialIoUartDebugMode = PchSerialIoSkipInit; |
| 220 | m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; |
| 221 | } |
| 222 | |
| 223 | static void fill_fspm_ipu_params(FSP_M_CONFIG *m_cfg, |
| 224 | const struct soc_intel_meteorlake_config *config) |
| 225 | { |
| 226 | /* Image clock: disable all clocks for bypassing FSP pin mux */ |
| 227 | memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn)); |
| 228 | /* IPU */ |
| 229 | m_cfg->SaIpuEnable = is_devfn_enabled(PCI_DEVFN_IPU); |
| 230 | } |
| 231 | |
| 232 | static void fill_fspm_smbus_params(FSP_M_CONFIG *m_cfg, |
| 233 | const struct soc_intel_meteorlake_config *config) |
| 234 | { |
| 235 | m_cfg->SmbusEnable = is_devfn_enabled(PCI_DEVFN_SMBUS); |
| 236 | } |
| 237 | |
Jay Patel | 310698c | 2023-06-01 14:01:43 -0700 | [diff] [blame] | 238 | static void fill_fspm_vr_config_params(FSP_M_CONFIG *m_cfg, |
| 239 | const struct soc_intel_meteorlake_config *config) |
| 240 | { |
| 241 | /* FastVmode Settings for VR domains */ |
| 242 | for (size_t domain = 0; domain < NUM_VR_DOMAINS; domain++) { |
Subrata Banik | 96f7bd1 | 2023-09-02 00:53:54 +0530 | [diff] [blame] | 243 | if (config->cep_enable[domain]) { |
| 244 | m_cfg->CepEnable[domain] = config->cep_enable[domain]; |
| 245 | if (config->enable_fast_vmode[domain]) { |
| 246 | m_cfg->EnableFastVmode[domain] = config->enable_fast_vmode[domain]; |
Jay Patel | 310698c | 2023-06-01 14:01:43 -0700 | [diff] [blame] | 247 | m_cfg->IccLimit[domain] = config->fast_vmode_i_trip[domain]; |
Subrata Banik | 96f7bd1 | 2023-09-02 00:53:54 +0530 | [diff] [blame] | 248 | } |
Jay Patel | 310698c | 2023-06-01 14:01:43 -0700 | [diff] [blame] | 249 | } |
Jeremy Compostella | a7a6522 | 2023-10-16 16:08:55 -0700 | [diff] [blame] | 250 | if (config->ps_cur_1_threshold[domain]) |
| 251 | m_cfg->Psi1Threshold[domain] = config->ps_cur_1_threshold[domain]; |
| 252 | if (config->ps_cur_2_threshold[domain]) |
| 253 | m_cfg->Psi2Threshold[domain] = config->ps_cur_2_threshold[domain]; |
| 254 | if (config->ps_cur_3_threshold[domain]) |
| 255 | m_cfg->Psi3Threshold[domain] = config->ps_cur_3_threshold[domain]; |
Jay Patel | 310698c | 2023-06-01 14:01:43 -0700 | [diff] [blame] | 256 | } |
| 257 | } |
| 258 | |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 259 | static void fill_fspm_misc_params(FSP_M_CONFIG *m_cfg, |
| 260 | const struct soc_intel_meteorlake_config *config) |
| 261 | { |
| 262 | /* Disable Lock PCU Thermal Management registers */ |
| 263 | m_cfg->LockPTMregs = 0; |
| 264 | |
| 265 | /* Skip CPU replacement check */ |
| 266 | m_cfg->SkipCpuReplacementCheck = !config->cpu_replacement_check; |
| 267 | |
| 268 | /* Skip GPIO configuration from FSP */ |
| 269 | m_cfg->GpioOverride = 0x1; |
Wonkyu Kim | e5f6ff8 | 2022-10-13 13:34:27 -0700 | [diff] [blame] | 270 | |
| 271 | /* Skip MBP HOB */ |
Kapil Porwal | e988cc2 | 2023-01-16 16:41:49 +0000 | [diff] [blame] | 272 | m_cfg->SkipMbpHob = !CONFIG(FSP_PUBLISH_MBP_HOB); |
Subrata Banik | f57eb1a | 2023-02-10 21:04:30 +0530 | [diff] [blame] | 273 | |
| 274 | m_cfg->SkipExtGfxScan = config->skip_ext_gfx_scan; |
Jakub Czapiga | bfadc78 | 2023-07-28 14:28:50 +0000 | [diff] [blame] | 275 | |
| 276 | /* Set PsysPmax if it is available in DT. |
| 277 | PsysPmax is in unit of 1/8 Watt */ |
| 278 | if (config->psys_pmax_watts) |
| 279 | m_cfg->PsysPmax = config->psys_pmax_watts * 8; |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 280 | } |
| 281 | |
| 282 | static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg, |
| 283 | const struct soc_intel_meteorlake_config *config) |
| 284 | { |
| 285 | /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ |
| 286 | m_cfg->PchHdaEnable = is_devfn_enabled(PCI_DEVFN_HDA); |
| 287 | m_cfg->PchHdaDspEnable = config->pch_hda_dsp_enable; |
| 288 | m_cfg->PchHdaIDispLinkTmode = config->pch_hda_idisp_link_tmode; |
| 289 | m_cfg->PchHdaIDispLinkFrequency = config->pch_hda_idisp_link_frequency; |
| 290 | m_cfg->PchHdaIDispCodecDisconnect = !config->pch_hda_idisp_codec_enable; |
Ronak Kanabar | b807a1d | 2023-05-31 10:28:51 +0530 | [diff] [blame] | 291 | |
| 292 | for (int i = 0; i < MAX_HD_AUDIO_SDI_LINKS; i++) |
| 293 | m_cfg->PchHdaSdiEnable[i] = config->pch_hda_sdi_enable[i]; |
| 294 | |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 295 | /* |
| 296 | * All the PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs are used by FSP only to |
| 297 | * configure GPIO pads for audio. Mainboard is expected to perform all GPIO |
| 298 | * configuration in coreboot and hence these UPDs are set to 0 to skip FSP GPIO |
| 299 | * configuration for audio pads. |
| 300 | */ |
| 301 | m_cfg->PchHdaAudioLinkHdaEnable = 0; |
| 302 | memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable)); |
| 303 | memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable)); |
| 304 | memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); |
| 305 | } |
| 306 | |
zhaojohn | a923a43 | 2022-09-22 20:33:57 -0700 | [diff] [blame] | 307 | static void fill_fspm_cnvi_params(FSP_M_CONFIG *m_cfg, |
| 308 | const struct soc_intel_meteorlake_config *config) |
| 309 | { |
| 310 | /* CNVi DDR RFI Mitigation */ |
| 311 | const struct device_path path[] = { |
| 312 | { .type = DEVICE_PATH_PCI, .pci.devfn = PCI_DEVFN_CNVI_WIFI }, |
| 313 | { .type = DEVICE_PATH_GENERIC, .generic.id = 0 } }; |
| 314 | const struct device *dev = find_dev_nested_path(pci_root_bus(), path, |
| 315 | ARRAY_SIZE(path)); |
| 316 | if (is_dev_enabled(dev)) |
| 317 | m_cfg->CnviDdrRfim = wifi_generic_cnvi_ddr_rfim_enabled(dev); |
| 318 | } |
| 319 | |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 320 | static void fill_fspm_ish_params(FSP_M_CONFIG *m_cfg, |
| 321 | const struct soc_intel_meteorlake_config *config) |
| 322 | { |
| 323 | m_cfg->PchIshEnable = is_devfn_enabled(PCI_DEVFN_ISH); |
| 324 | } |
| 325 | |
| 326 | static void fill_fspm_tcss_params(FSP_M_CONFIG *m_cfg, |
| 327 | const struct soc_intel_meteorlake_config *config) |
| 328 | { |
| 329 | int i, max_port; |
| 330 | |
| 331 | /* Tcss USB */ |
| 332 | m_cfg->TcssXhciEn = is_devfn_enabled(PCI_DEVFN_TCSS_XHCI); |
| 333 | m_cfg->TcssXdciEn = is_devfn_enabled(PCI_DEVFN_TCSS_XDCI); |
| 334 | |
| 335 | /* TCSS DMA */ |
| 336 | m_cfg->TcssDma0En = is_devfn_enabled(PCI_DEVFN_TCSS_DMA0); |
Ivy Jian | 4257e8c | 2022-09-12 14:42:58 +0800 | [diff] [blame] | 337 | m_cfg->TcssDma1En = is_devfn_enabled(PCI_DEVFN_TCSS_DMA1); |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 338 | |
| 339 | /* Enable TCSS port */ |
| 340 | max_port = get_max_tcss_port(); |
| 341 | m_cfg->UsbTcPortEnPreMem = 0; |
| 342 | for (i = 0; i < max_port; i++) |
| 343 | if (config->tcss_ports[i].enable) |
| 344 | m_cfg->UsbTcPortEnPreMem |= BIT(i); |
| 345 | } |
| 346 | |
| 347 | static void fill_fspm_usb4_params(FSP_M_CONFIG *m_cfg, |
| 348 | const struct soc_intel_meteorlake_config *config) |
| 349 | { |
Sridhar Siricilla | cb4d464 | 2022-09-26 12:12:20 +0530 | [diff] [blame] | 350 | m_cfg->TcssItbtPcie0En = is_devfn_enabled(PCI_DEVFN_TBT0); |
| 351 | m_cfg->TcssItbtPcie1En = is_devfn_enabled(PCI_DEVFN_TBT1); |
| 352 | m_cfg->TcssItbtPcie2En = is_devfn_enabled(PCI_DEVFN_TBT2); |
| 353 | m_cfg->TcssItbtPcie3En = is_devfn_enabled(PCI_DEVFN_TBT3); |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 354 | } |
| 355 | |
| 356 | static void fill_fspm_vtd_params(FSP_M_CONFIG *m_cfg, |
| 357 | const struct soc_intel_meteorlake_config *config) |
| 358 | { |
| 359 | m_cfg->VtdDisable = 0; |
| 360 | m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; |
| 361 | m_cfg->VtdBaseAddress[1] = VTVC0_BASE_ADDRESS; |
| 362 | |
| 363 | /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ |
| 364 | m_cfg->VmxEnable = CONFIG(ENABLE_VMX); |
| 365 | } |
| 366 | |
| 367 | static void fill_fspm_trace_params(FSP_M_CONFIG *m_cfg, |
| 368 | const struct soc_intel_meteorlake_config *config) |
| 369 | { |
| 370 | /* Set debug probe type */ |
vjadeja-intel | 0ddeaed | 2022-11-03 14:48:46 +0530 | [diff] [blame] | 371 | m_cfg->PlatformDebugOption = CONFIG_SOC_INTEL_METEORLAKE_DEBUG_CONSENT; |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 372 | |
| 373 | /* CrashLog config */ |
| 374 | if (CONFIG(SOC_INTEL_CRASHLOG)) { |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 375 | m_cfg->CpuCrashLogEnable = 1; |
| 376 | } |
| 377 | } |
| 378 | |
Marx Wang | be0e694 | 2023-10-19 15:15:22 +0800 | [diff] [blame] | 379 | static void fill_fspm_ibecc_params(FSP_M_CONFIG *m_cfg, |
| 380 | const struct soc_intel_meteorlake_config *config) |
| 381 | { |
| 382 | /* In-Band ECC configuration */ |
| 383 | if (config->ibecc.enable) { |
| 384 | m_cfg->Ibecc = config->ibecc.enable; |
| 385 | m_cfg->IbeccParity = config->ibecc.parity_en; |
| 386 | m_cfg->IbeccOperationMode = config->ibecc.mode; |
| 387 | if (m_cfg->IbeccOperationMode == IBECC_MODE_PER_REGION) { |
| 388 | FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRegionEnable, |
| 389 | config->ibecc.region_enable); |
| 390 | FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRegionBase, |
| 391 | config->ibecc.region_base); |
| 392 | FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRegionMask, |
| 393 | config->ibecc.region_mask); |
| 394 | } |
| 395 | } |
| 396 | } |
| 397 | |
Subrata Banik | 26fdb06 | 2023-11-28 20:36:45 +0530 | [diff] [blame^] | 398 | static void fill_fsps_acoustic_params(FSP_M_CONFIG *m_cfg, |
| 399 | const struct soc_intel_meteorlake_config *config) |
| 400 | { |
| 401 | if (!config->enable_acoustic_noise_mitigation) |
| 402 | return; |
| 403 | |
| 404 | m_cfg->AcousticNoiseMitigation = config->enable_acoustic_noise_mitigation; |
| 405 | |
| 406 | for (int i = 0; i < NUM_VR_DOMAINS; i++) { |
| 407 | m_cfg->FastPkgCRampDisable[i] = config->disable_fast_pkgc_ramp[i]; |
| 408 | m_cfg->SlowSlewRate[i] = config->slow_slew_rate_config[i]; |
| 409 | } |
| 410 | } |
| 411 | |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 412 | static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, |
| 413 | const struct soc_intel_meteorlake_config *config) |
| 414 | { |
Arthur Heymans | 4081d6c | 2022-07-29 10:45:52 +0200 | [diff] [blame] | 415 | void (*fill_fspm_params[])(FSP_M_CONFIG *m_cfg, |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 416 | const struct soc_intel_meteorlake_config *config) = { |
| 417 | fill_fspm_igd_params, |
| 418 | fill_fspm_mrc_params, |
| 419 | fill_fspm_cpu_params, |
| 420 | fill_fspm_security_params, |
| 421 | fill_fspm_uart_params, |
| 422 | fill_fspm_ipu_params, |
| 423 | fill_fspm_smbus_params, |
| 424 | fill_fspm_misc_params, |
| 425 | fill_fspm_audio_params, |
zhaojohn | a923a43 | 2022-09-22 20:33:57 -0700 | [diff] [blame] | 426 | fill_fspm_cnvi_params, |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 427 | fill_fspm_pcie_rp_params, |
| 428 | fill_fspm_ish_params, |
| 429 | fill_fspm_tcss_params, |
| 430 | fill_fspm_usb4_params, |
| 431 | fill_fspm_vtd_params, |
| 432 | fill_fspm_trace_params, |
Jay Patel | 310698c | 2023-06-01 14:01:43 -0700 | [diff] [blame] | 433 | fill_fspm_vr_config_params, |
Marx Wang | be0e694 | 2023-10-19 15:15:22 +0800 | [diff] [blame] | 434 | fill_fspm_ibecc_params, |
Subrata Banik | 26fdb06 | 2023-11-28 20:36:45 +0530 | [diff] [blame^] | 435 | fill_fsps_acoustic_params, |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 436 | }; |
| 437 | |
| 438 | for (size_t i = 0; i < ARRAY_SIZE(fill_fspm_params); i++) |
| 439 | fill_fspm_params[i](m_cfg, config); |
| 440 | } |
| 441 | |
Jeremy Compostella | 79c09ba | 2023-10-20 14:06:36 -0700 | [diff] [blame] | 442 | #define UX_MEMORY_TRAINING_DESC "memory_training_desc" |
| 443 | |
| 444 | #define VGA_INIT_CONTROL_ENABLE BIT(0) |
| 445 | /* Tear down legacy VGA mode before exiting FSP-M. */ |
| 446 | #define VGA_INIT_CONTROL_TEAR_DOWN BIT(1) |
| 447 | |
| 448 | static void fill_fspm_sign_of_life(FSP_M_CONFIG *m_cfg, |
| 449 | FSPM_ARCH_UPD *arch_upd) |
| 450 | { |
| 451 | void *vbt; |
| 452 | size_t vbt_size; |
| 453 | uint32_t vga_init_control = 0; |
Subrata Banik | 7ae5100 | 2023-11-09 14:42:04 +0530 | [diff] [blame] | 454 | uint8_t sol_type; |
Jeremy Compostella | 79c09ba | 2023-10-20 14:06:36 -0700 | [diff] [blame] | 455 | |
| 456 | /* Memory training. */ |
Subrata Banik | 7ae5100 | 2023-11-09 14:42:04 +0530 | [diff] [blame] | 457 | if (!arch_upd->NvsBufferPtr) { |
Jeremy Compostella | 79c09ba | 2023-10-20 14:06:36 -0700 | [diff] [blame] | 458 | vga_init_control = VGA_INIT_CONTROL_ENABLE | |
| 459 | VGA_INIT_CONTROL_TEAR_DOWN; |
Subrata Banik | 7ae5100 | 2023-11-09 14:42:04 +0530 | [diff] [blame] | 460 | sol_type = ELOG_FW_EARLY_SOL_MRC; |
| 461 | } |
Jeremy Compostella | 79c09ba | 2023-10-20 14:06:36 -0700 | [diff] [blame] | 462 | |
Subrata Banik | 7ae5100 | 2023-11-09 14:42:04 +0530 | [diff] [blame] | 463 | if (is_cse_fw_update_required()) { |
Jeremy Compostella | 79c09ba | 2023-10-20 14:06:36 -0700 | [diff] [blame] | 464 | vga_init_control = VGA_INIT_CONTROL_ENABLE; |
Subrata Banik | 7ae5100 | 2023-11-09 14:42:04 +0530 | [diff] [blame] | 465 | sol_type = ELOG_FW_EARLY_SOL_CSE_SYNC; |
| 466 | } |
Jeremy Compostella | 79c09ba | 2023-10-20 14:06:36 -0700 | [diff] [blame] | 467 | |
| 468 | if (!vga_init_control) |
| 469 | return; |
| 470 | |
| 471 | const char *text = ux_locales_get_text(UX_MEMORY_TRAINING_DESC); |
| 472 | /* No localized text found; fallback to built-in English. */ |
| 473 | if (!text) |
| 474 | text = "Your device is finishing an update. " |
| 475 | "This may take 1-2 minutes.\n" |
| 476 | "Please do not turn off your device."; |
| 477 | |
| 478 | vbt = cbfs_map("vbt.bin", &vbt_size); |
| 479 | if (!vbt) { |
| 480 | printk(BIOS_ERR, "Could not load vbt.bin\n"); |
| 481 | return; |
| 482 | } |
| 483 | |
| 484 | printk(BIOS_INFO, "Enabling FSP-M Sign-of-Life\n"); |
Subrata Banik | 7ae5100 | 2023-11-09 14:42:04 +0530 | [diff] [blame] | 485 | elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, sol_type); |
Jeremy Compostella | 79c09ba | 2023-10-20 14:06:36 -0700 | [diff] [blame] | 486 | |
| 487 | m_cfg->VgaInitControl = vga_init_control; |
| 488 | m_cfg->VbtPtr = (UINT32)vbt; |
| 489 | m_cfg->VbtSize = vbt_size; |
| 490 | m_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP); |
| 491 | m_cfg->VgaMessage = (UINT32)text; |
| 492 | } |
| 493 | |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 494 | void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |
| 495 | { |
| 496 | const struct soc_intel_meteorlake_config *config; |
| 497 | FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; |
Subrata Banik | e88bee7 | 2022-06-27 16:51:44 +0530 | [diff] [blame] | 498 | FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 499 | |
Subrata Banik | e88bee7 | 2022-06-27 16:51:44 +0530 | [diff] [blame] | 500 | if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER)) { |
| 501 | if (CONFIG(CONSOLE_SERIAL) && CONFIG(FSP_ENABLE_SERIAL_DEBUG)) { |
| 502 | enum fsp_log_level log_level = fsp_map_console_log_level(); |
| 503 | arch_upd->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *) |
| 504 | fsp_debug_event_handler); |
| 505 | /* Set Serial debug message level */ |
| 506 | m_cfg->PcdSerialDebugLevel = log_level; |
| 507 | /* Set MRC debug level */ |
| 508 | m_cfg->SerialDebugMrcLevel = log_level; |
| 509 | } else { |
| 510 | /* Disable Serial debug message */ |
| 511 | m_cfg->PcdSerialDebugLevel = 0; |
| 512 | /* Disable MRC debug message */ |
| 513 | m_cfg->SerialDebugMrcLevel = 0; |
| 514 | } |
| 515 | } |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 516 | config = config_of_soc(); |
| 517 | |
| 518 | soc_memory_init_params(m_cfg, config); |
Jeremy Compostella | 79c09ba | 2023-10-20 14:06:36 -0700 | [diff] [blame] | 519 | |
| 520 | if (CONFIG(SOC_INTEL_METEORLAKE_SIGN_OF_LIFE)) |
| 521 | fill_fspm_sign_of_life(m_cfg, arch_upd); |
| 522 | |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 523 | mainboard_memory_init_params(mupd); |
| 524 | } |
| 525 | |
| 526 | __weak void mainboard_memory_init_params(FSPM_UPD *memupd) |
| 527 | { |
| 528 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 529 | } |