Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <assert.h> |
| 4 | #include <console/console.h> |
Subrata Banik | a3ad319 | 2022-09-08 09:38:08 -0700 | [diff] [blame] | 5 | #include <cpu/intel/cpu_ids.h> |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 6 | #include <cpu/x86/msr.h> |
| 7 | #include <device/device.h> |
zhaojohn | a923a43 | 2022-09-22 20:33:57 -0700 | [diff] [blame] | 8 | #include <drivers/wifi/generic/wifi.h> |
Subrata Banik | e88bee7 | 2022-06-27 16:51:44 +0530 | [diff] [blame] | 9 | #include <fsp/fsp_debug_event.h> |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 10 | #include <fsp/util.h> |
| 11 | #include <intelblocks/cpulib.h> |
| 12 | #include <intelblocks/pcie_rp.h> |
| 13 | #include <soc/gpio_soc_defs.h> |
| 14 | #include <soc/iomap.h> |
| 15 | #include <soc/msr.h> |
| 16 | #include <soc/pci_devs.h> |
| 17 | #include <soc/pcie.h> |
| 18 | #include <soc/romstage.h> |
| 19 | #include <soc/soc_chip.h> |
| 20 | #include <soc/soc_info.h> |
| 21 | #include <string.h> |
| 22 | |
| 23 | #define FSP_CLK_NOTUSED 0xFF |
| 24 | #define FSP_CLK_LAN 0x70 |
| 25 | #define FSP_CLK_FREE_RUNNING 0x80 |
| 26 | |
| 27 | static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, |
| 28 | const struct pcie_rp_config *cfg, size_t cfg_count) |
| 29 | { |
| 30 | size_t i; |
Subrata Banik | 3eac049 | 2022-12-06 13:48:44 +0530 | [diff] [blame] | 31 | static unsigned int clk_req_mapping = 0; |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 32 | |
| 33 | for (i = 0; i < cfg_count; i++) { |
Subrata Banik | c0f4b12 | 2022-12-06 14:03:07 +0530 | [diff] [blame] | 34 | if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) { |
| 35 | m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING; |
| 36 | continue; |
| 37 | } |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 38 | if (!(en_mask & BIT(i))) |
| 39 | continue; |
| 40 | if (cfg[i].flags & PCIE_RP_CLK_SRC_UNUSED) |
| 41 | continue; |
Subrata Banik | 64dd9d0 | 2022-12-06 13:55:01 +0530 | [diff] [blame] | 42 | if (!cfg[i].flags && cfg[i].clk_src == 0 && cfg[i].clk_req == 0) { |
| 43 | printk(BIOS_WARNING, "Missing root port clock structure definition\n"); |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 44 | continue; |
Subrata Banik | 64dd9d0 | 2022-12-06 13:55:01 +0530 | [diff] [blame] | 45 | } |
Subrata Banik | 3eac049 | 2022-12-06 13:48:44 +0530 | [diff] [blame] | 46 | if (clk_req_mapping & (1 << cfg[i].clk_req)) |
| 47 | printk(BIOS_WARNING, "Found overlapped clkreq assignment on clk req %d\n" |
| 48 | , cfg[i].clk_req); |
| 49 | if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED)) { |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 50 | m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req; |
Subrata Banik | 3eac049 | 2022-12-06 13:48:44 +0530 | [diff] [blame] | 51 | clk_req_mapping |= 1 << cfg[i].clk_req; |
| 52 | } |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 53 | m_cfg->PcieClkSrcUsage[cfg[i].clk_src] = i; |
| 54 | } |
| 55 | } |
| 56 | |
| 57 | static void fill_fspm_pcie_rp_params(FSP_M_CONFIG *m_cfg, |
| 58 | const struct soc_intel_meteorlake_config *config) |
| 59 | { |
| 60 | /* Disable all PCIe clock sources by default. And set RP irrelevant clock. */ |
| 61 | unsigned int i; |
| 62 | uint8_t max_clock = get_max_pcie_clock(); |
| 63 | |
| 64 | for (i = 0; i < max_clock; i++) { |
| 65 | if (config->pcie_clk_config_flag[i] & PCIE_CLK_FREE_RUNNING) |
| 66 | m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING; |
| 67 | else if (config->pcie_clk_config_flag[i] & PCIE_CLK_LAN) |
| 68 | m_cfg->PcieClkSrcUsage[i] = FSP_CLK_LAN; |
| 69 | else |
| 70 | m_cfg->PcieClkSrcUsage[i] = FSP_CLK_NOTUSED; |
| 71 | m_cfg->PcieClkSrcClkReq[i] = FSP_CLK_NOTUSED; |
| 72 | } |
| 73 | |
| 74 | /* PCIE ports */ |
| 75 | m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pcie_rp_table()); |
| 76 | pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, config->pcie_rp, |
| 77 | get_max_pcie_port()); |
| 78 | } |
| 79 | |
| 80 | static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg, |
| 81 | const struct soc_intel_meteorlake_config *config) |
| 82 | { |
| 83 | unsigned int i; |
| 84 | const struct ddi_port_upds { |
| 85 | uint8_t *ddc; |
| 86 | uint8_t *hpd; |
| 87 | } ddi_port_upds[] = { |
| 88 | [DDI_PORT_A] = {&m_cfg->DdiPortADdc, &m_cfg->DdiPortAHpd}, |
| 89 | [DDI_PORT_B] = {&m_cfg->DdiPortBDdc, &m_cfg->DdiPortBHpd}, |
| 90 | [DDI_PORT_C] = {&m_cfg->DdiPortCDdc, &m_cfg->DdiPortCHpd}, |
| 91 | [DDI_PORT_1] = {&m_cfg->DdiPort1Ddc, &m_cfg->DdiPort1Hpd}, |
| 92 | [DDI_PORT_2] = {&m_cfg->DdiPort2Ddc, &m_cfg->DdiPort2Hpd}, |
| 93 | [DDI_PORT_3] = {&m_cfg->DdiPort3Ddc, &m_cfg->DdiPort3Hpd}, |
| 94 | [DDI_PORT_4] = {&m_cfg->DdiPort4Ddc, &m_cfg->DdiPort4Hpd}, |
| 95 | }; |
| 96 | m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(PCI_DEVFN_IGD); |
| 97 | if (m_cfg->InternalGfx) { |
| 98 | /* IGD is enabled, set IGD stolen size to 64MB. */ |
| 99 | m_cfg->IgdDvmt50PreAlloc = IGD_SM_64MB; |
| 100 | /* DP port config */ |
| 101 | m_cfg->DdiPortAConfig = config->ddi_port_A_config; |
| 102 | m_cfg->DdiPortBConfig = config->ddi_port_B_config; |
| 103 | for (i = 0; i < ARRAY_SIZE(ddi_port_upds); i++) { |
| 104 | *ddi_port_upds[i].ddc = !!(config->ddi_ports_config[i] & |
| 105 | DDI_ENABLE_DDC); |
| 106 | *ddi_port_upds[i].hpd = !!(config->ddi_ports_config[i] & |
| 107 | DDI_ENABLE_HPD); |
| 108 | } |
| 109 | } else { |
| 110 | /* IGD is disabled, skip IGD init in FSP. */ |
| 111 | m_cfg->IgdDvmt50PreAlloc = 0; |
| 112 | /* DP port config */ |
| 113 | m_cfg->DdiPortAConfig = 0; |
| 114 | m_cfg->DdiPortBConfig = 0; |
| 115 | for (i = 0; i < ARRAY_SIZE(ddi_port_upds); i++) { |
| 116 | *ddi_port_upds[i].ddc = 0; |
| 117 | *ddi_port_upds[i].hpd = 0; |
| 118 | } |
| 119 | } |
| 120 | } |
| 121 | |
| 122 | static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg, |
| 123 | const struct soc_intel_meteorlake_config *config) |
| 124 | { |
Subrata Banik | 289f9a5 | 2023-01-20 21:38:05 +0530 | [diff] [blame^] | 125 | m_cfg->SaGv = config->sagv; |
| 126 | m_cfg->RMT = config->rmt; |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 127 | } |
| 128 | |
| 129 | static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg, |
| 130 | const struct soc_intel_meteorlake_config *config) |
| 131 | { |
| 132 | m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; |
| 133 | /* CpuRatio Settings */ |
| 134 | if (config->cpu_ratio_override) |
| 135 | m_cfg->CpuRatio = config->cpu_ratio_override; |
| 136 | else |
| 137 | /* Set CpuRatio to match existing MSR value */ |
| 138 | m_cfg->CpuRatio = (rdmsr(MSR_FLEX_RATIO).lo >> 8) & 0xff; |
| 139 | |
| 140 | m_cfg->PrmrrSize = get_valid_prmrr_size(); |
| 141 | /* Enable Hyper Threading */ |
| 142 | m_cfg->HyperThreading = 1; |
| 143 | } |
| 144 | |
| 145 | static void fill_fspm_security_params(FSP_M_CONFIG *m_cfg, |
| 146 | const struct soc_intel_meteorlake_config *config) |
| 147 | { |
| 148 | /* Disable BIOS Guard */ |
| 149 | m_cfg->BiosGuard = 0; |
Subrata Banik | 1e71fe1 | 2022-08-15 15:40:59 +0530 | [diff] [blame] | 150 | m_cfg->TmeEnable = CONFIG(INTEL_TME) && is_tme_supported(); |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 151 | } |
| 152 | |
| 153 | static void fill_fspm_uart_params(FSP_M_CONFIG *m_cfg, |
| 154 | const struct soc_intel_meteorlake_config *config) |
| 155 | { |
| 156 | if (CONFIG(DRIVERS_UART_8250IO)) |
| 157 | m_cfg->PcdIsaSerialUartBase = ISA_SERIAL_BASE_ADDR_3F8; |
| 158 | m_cfg->SerialIoUartDebugMode = PchSerialIoSkipInit; |
| 159 | m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; |
| 160 | } |
| 161 | |
| 162 | static void fill_fspm_ipu_params(FSP_M_CONFIG *m_cfg, |
| 163 | const struct soc_intel_meteorlake_config *config) |
| 164 | { |
| 165 | /* Image clock: disable all clocks for bypassing FSP pin mux */ |
| 166 | memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn)); |
| 167 | /* IPU */ |
| 168 | m_cfg->SaIpuEnable = is_devfn_enabled(PCI_DEVFN_IPU); |
| 169 | } |
| 170 | |
| 171 | static void fill_fspm_smbus_params(FSP_M_CONFIG *m_cfg, |
| 172 | const struct soc_intel_meteorlake_config *config) |
| 173 | { |
| 174 | m_cfg->SmbusEnable = is_devfn_enabled(PCI_DEVFN_SMBUS); |
| 175 | } |
| 176 | |
| 177 | static void fill_fspm_misc_params(FSP_M_CONFIG *m_cfg, |
| 178 | const struct soc_intel_meteorlake_config *config) |
| 179 | { |
| 180 | /* Disable Lock PCU Thermal Management registers */ |
| 181 | m_cfg->LockPTMregs = 0; |
| 182 | |
| 183 | /* Skip CPU replacement check */ |
| 184 | m_cfg->SkipCpuReplacementCheck = !config->cpu_replacement_check; |
| 185 | |
| 186 | /* Skip GPIO configuration from FSP */ |
| 187 | m_cfg->GpioOverride = 0x1; |
Wonkyu Kim | e5f6ff8 | 2022-10-13 13:34:27 -0700 | [diff] [blame] | 188 | |
| 189 | /* Skip MBP HOB */ |
Kapil Porwal | e988cc2 | 2023-01-16 16:41:49 +0000 | [diff] [blame] | 190 | m_cfg->SkipMbpHob = !CONFIG(FSP_PUBLISH_MBP_HOB); |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 191 | } |
| 192 | |
| 193 | static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg, |
| 194 | const struct soc_intel_meteorlake_config *config) |
| 195 | { |
| 196 | /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ |
| 197 | m_cfg->PchHdaEnable = is_devfn_enabled(PCI_DEVFN_HDA); |
| 198 | m_cfg->PchHdaDspEnable = config->pch_hda_dsp_enable; |
| 199 | m_cfg->PchHdaIDispLinkTmode = config->pch_hda_idisp_link_tmode; |
| 200 | m_cfg->PchHdaIDispLinkFrequency = config->pch_hda_idisp_link_frequency; |
| 201 | m_cfg->PchHdaIDispCodecDisconnect = !config->pch_hda_idisp_codec_enable; |
| 202 | /* |
| 203 | * All the PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs are used by FSP only to |
| 204 | * configure GPIO pads for audio. Mainboard is expected to perform all GPIO |
| 205 | * configuration in coreboot and hence these UPDs are set to 0 to skip FSP GPIO |
| 206 | * configuration for audio pads. |
| 207 | */ |
| 208 | m_cfg->PchHdaAudioLinkHdaEnable = 0; |
| 209 | memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable)); |
| 210 | memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable)); |
| 211 | memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); |
| 212 | } |
| 213 | |
zhaojohn | a923a43 | 2022-09-22 20:33:57 -0700 | [diff] [blame] | 214 | static void fill_fspm_cnvi_params(FSP_M_CONFIG *m_cfg, |
| 215 | const struct soc_intel_meteorlake_config *config) |
| 216 | { |
| 217 | /* CNVi DDR RFI Mitigation */ |
| 218 | const struct device_path path[] = { |
| 219 | { .type = DEVICE_PATH_PCI, .pci.devfn = PCI_DEVFN_CNVI_WIFI }, |
| 220 | { .type = DEVICE_PATH_GENERIC, .generic.id = 0 } }; |
| 221 | const struct device *dev = find_dev_nested_path(pci_root_bus(), path, |
| 222 | ARRAY_SIZE(path)); |
| 223 | if (is_dev_enabled(dev)) |
| 224 | m_cfg->CnviDdrRfim = wifi_generic_cnvi_ddr_rfim_enabled(dev); |
| 225 | } |
| 226 | |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 227 | static void fill_fspm_ish_params(FSP_M_CONFIG *m_cfg, |
| 228 | const struct soc_intel_meteorlake_config *config) |
| 229 | { |
| 230 | m_cfg->PchIshEnable = is_devfn_enabled(PCI_DEVFN_ISH); |
| 231 | } |
| 232 | |
| 233 | static void fill_fspm_tcss_params(FSP_M_CONFIG *m_cfg, |
| 234 | const struct soc_intel_meteorlake_config *config) |
| 235 | { |
| 236 | int i, max_port; |
| 237 | |
| 238 | /* Tcss USB */ |
| 239 | m_cfg->TcssXhciEn = is_devfn_enabled(PCI_DEVFN_TCSS_XHCI); |
| 240 | m_cfg->TcssXdciEn = is_devfn_enabled(PCI_DEVFN_TCSS_XDCI); |
| 241 | |
| 242 | /* TCSS DMA */ |
| 243 | m_cfg->TcssDma0En = is_devfn_enabled(PCI_DEVFN_TCSS_DMA0); |
Ivy Jian | 4257e8c | 2022-09-12 14:42:58 +0800 | [diff] [blame] | 244 | m_cfg->TcssDma1En = is_devfn_enabled(PCI_DEVFN_TCSS_DMA1); |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 245 | |
| 246 | /* Enable TCSS port */ |
| 247 | max_port = get_max_tcss_port(); |
| 248 | m_cfg->UsbTcPortEnPreMem = 0; |
| 249 | for (i = 0; i < max_port; i++) |
| 250 | if (config->tcss_ports[i].enable) |
| 251 | m_cfg->UsbTcPortEnPreMem |= BIT(i); |
| 252 | } |
| 253 | |
| 254 | static void fill_fspm_usb4_params(FSP_M_CONFIG *m_cfg, |
| 255 | const struct soc_intel_meteorlake_config *config) |
| 256 | { |
Sridhar Siricilla | cb4d464 | 2022-09-26 12:12:20 +0530 | [diff] [blame] | 257 | m_cfg->TcssItbtPcie0En = is_devfn_enabled(PCI_DEVFN_TBT0); |
| 258 | m_cfg->TcssItbtPcie1En = is_devfn_enabled(PCI_DEVFN_TBT1); |
| 259 | m_cfg->TcssItbtPcie2En = is_devfn_enabled(PCI_DEVFN_TBT2); |
| 260 | m_cfg->TcssItbtPcie3En = is_devfn_enabled(PCI_DEVFN_TBT3); |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 261 | } |
| 262 | |
| 263 | static void fill_fspm_vtd_params(FSP_M_CONFIG *m_cfg, |
| 264 | const struct soc_intel_meteorlake_config *config) |
| 265 | { |
| 266 | m_cfg->VtdDisable = 0; |
| 267 | m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; |
| 268 | m_cfg->VtdBaseAddress[1] = VTVC0_BASE_ADDRESS; |
| 269 | |
| 270 | /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ |
| 271 | m_cfg->VmxEnable = CONFIG(ENABLE_VMX); |
| 272 | } |
| 273 | |
| 274 | static void fill_fspm_trace_params(FSP_M_CONFIG *m_cfg, |
| 275 | const struct soc_intel_meteorlake_config *config) |
| 276 | { |
| 277 | /* Set debug probe type */ |
vjadeja-intel | 0ddeaed | 2022-11-03 14:48:46 +0530 | [diff] [blame] | 278 | m_cfg->PlatformDebugOption = CONFIG_SOC_INTEL_METEORLAKE_DEBUG_CONSENT; |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 279 | |
| 280 | /* CrashLog config */ |
| 281 | if (CONFIG(SOC_INTEL_CRASHLOG)) { |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 282 | m_cfg->CpuCrashLogEnable = 1; |
| 283 | } |
| 284 | } |
| 285 | |
| 286 | static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, |
| 287 | const struct soc_intel_meteorlake_config *config) |
| 288 | { |
Arthur Heymans | 4081d6c | 2022-07-29 10:45:52 +0200 | [diff] [blame] | 289 | void (*fill_fspm_params[])(FSP_M_CONFIG *m_cfg, |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 290 | const struct soc_intel_meteorlake_config *config) = { |
| 291 | fill_fspm_igd_params, |
| 292 | fill_fspm_mrc_params, |
| 293 | fill_fspm_cpu_params, |
| 294 | fill_fspm_security_params, |
| 295 | fill_fspm_uart_params, |
| 296 | fill_fspm_ipu_params, |
| 297 | fill_fspm_smbus_params, |
| 298 | fill_fspm_misc_params, |
| 299 | fill_fspm_audio_params, |
zhaojohn | a923a43 | 2022-09-22 20:33:57 -0700 | [diff] [blame] | 300 | fill_fspm_cnvi_params, |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 301 | fill_fspm_pcie_rp_params, |
| 302 | fill_fspm_ish_params, |
| 303 | fill_fspm_tcss_params, |
| 304 | fill_fspm_usb4_params, |
| 305 | fill_fspm_vtd_params, |
| 306 | fill_fspm_trace_params, |
| 307 | }; |
| 308 | |
| 309 | for (size_t i = 0; i < ARRAY_SIZE(fill_fspm_params); i++) |
| 310 | fill_fspm_params[i](m_cfg, config); |
| 311 | } |
| 312 | |
| 313 | void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |
| 314 | { |
| 315 | const struct soc_intel_meteorlake_config *config; |
| 316 | FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; |
Subrata Banik | e88bee7 | 2022-06-27 16:51:44 +0530 | [diff] [blame] | 317 | FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 318 | |
Subrata Banik | e88bee7 | 2022-06-27 16:51:44 +0530 | [diff] [blame] | 319 | if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER)) { |
| 320 | if (CONFIG(CONSOLE_SERIAL) && CONFIG(FSP_ENABLE_SERIAL_DEBUG)) { |
| 321 | enum fsp_log_level log_level = fsp_map_console_log_level(); |
| 322 | arch_upd->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *) |
| 323 | fsp_debug_event_handler); |
| 324 | /* Set Serial debug message level */ |
| 325 | m_cfg->PcdSerialDebugLevel = log_level; |
| 326 | /* Set MRC debug level */ |
| 327 | m_cfg->SerialDebugMrcLevel = log_level; |
| 328 | } else { |
| 329 | /* Disable Serial debug message */ |
| 330 | m_cfg->PcdSerialDebugLevel = 0; |
| 331 | /* Disable MRC debug message */ |
| 332 | m_cfg->SerialDebugMrcLevel = 0; |
| 333 | } |
| 334 | } |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 335 | config = config_of_soc(); |
| 336 | |
| 337 | soc_memory_init_params(m_cfg, config); |
| 338 | mainboard_memory_init_params(mupd); |
| 339 | } |
| 340 | |
| 341 | __weak void mainboard_memory_init_params(FSPM_UPD *memupd) |
| 342 | { |
| 343 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 344 | } |