Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <assert.h> |
| 4 | #include <console/console.h> |
Subrata Banik | a3ad319 | 2022-09-08 09:38:08 -0700 | [diff] [blame] | 5 | #include <cpu/intel/cpu_ids.h> |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 6 | #include <cpu/x86/msr.h> |
| 7 | #include <device/device.h> |
zhaojohn | a923a43 | 2022-09-22 20:33:57 -0700 | [diff] [blame] | 8 | #include <drivers/wifi/generic/wifi.h> |
Subrata Banik | e88bee7 | 2022-06-27 16:51:44 +0530 | [diff] [blame] | 9 | #include <fsp/fsp_debug_event.h> |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 10 | #include <fsp/util.h> |
Pratikkumar Prajapati | 10bd2a2 | 2023-06-05 18:18:16 -0700 | [diff] [blame] | 11 | #include <intelbasecode/ramtop.h> |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 12 | #include <intelblocks/cpulib.h> |
| 13 | #include <intelblocks/pcie_rp.h> |
Eran Mitrani | 222903e | 2022-12-19 11:27:10 -0800 | [diff] [blame] | 14 | #include <option.h> |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 15 | #include <soc/gpio_soc_defs.h> |
| 16 | #include <soc/iomap.h> |
| 17 | #include <soc/msr.h> |
| 18 | #include <soc/pci_devs.h> |
| 19 | #include <soc/pcie.h> |
| 20 | #include <soc/romstage.h> |
| 21 | #include <soc/soc_chip.h> |
| 22 | #include <soc/soc_info.h> |
| 23 | #include <string.h> |
| 24 | |
| 25 | #define FSP_CLK_NOTUSED 0xFF |
| 26 | #define FSP_CLK_LAN 0x70 |
| 27 | #define FSP_CLK_FREE_RUNNING 0x80 |
| 28 | |
| 29 | static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, |
| 30 | const struct pcie_rp_config *cfg, size_t cfg_count) |
| 31 | { |
| 32 | size_t i; |
Subrata Banik | 3eac049 | 2022-12-06 13:48:44 +0530 | [diff] [blame] | 33 | static unsigned int clk_req_mapping = 0; |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 34 | |
| 35 | for (i = 0; i < cfg_count; i++) { |
Subrata Banik | c0f4b12 | 2022-12-06 14:03:07 +0530 | [diff] [blame] | 36 | if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) { |
| 37 | m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING; |
| 38 | continue; |
| 39 | } |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 40 | if (!(en_mask & BIT(i))) |
| 41 | continue; |
| 42 | if (cfg[i].flags & PCIE_RP_CLK_SRC_UNUSED) |
| 43 | continue; |
Subrata Banik | 64dd9d0 | 2022-12-06 13:55:01 +0530 | [diff] [blame] | 44 | if (!cfg[i].flags && cfg[i].clk_src == 0 && cfg[i].clk_req == 0) { |
| 45 | printk(BIOS_WARNING, "Missing root port clock structure definition\n"); |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 46 | continue; |
Subrata Banik | 64dd9d0 | 2022-12-06 13:55:01 +0530 | [diff] [blame] | 47 | } |
Subrata Banik | 3eac049 | 2022-12-06 13:48:44 +0530 | [diff] [blame] | 48 | if (clk_req_mapping & (1 << cfg[i].clk_req)) |
| 49 | printk(BIOS_WARNING, "Found overlapped clkreq assignment on clk req %d\n" |
| 50 | , cfg[i].clk_req); |
| 51 | if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED)) { |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 52 | m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req; |
Subrata Banik | 3eac049 | 2022-12-06 13:48:44 +0530 | [diff] [blame] | 53 | clk_req_mapping |= 1 << cfg[i].clk_req; |
| 54 | } |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 55 | m_cfg->PcieClkSrcUsage[cfg[i].clk_src] = i; |
| 56 | } |
| 57 | } |
| 58 | |
| 59 | static void fill_fspm_pcie_rp_params(FSP_M_CONFIG *m_cfg, |
| 60 | const struct soc_intel_meteorlake_config *config) |
| 61 | { |
| 62 | /* Disable all PCIe clock sources by default. And set RP irrelevant clock. */ |
| 63 | unsigned int i; |
| 64 | uint8_t max_clock = get_max_pcie_clock(); |
| 65 | |
| 66 | for (i = 0; i < max_clock; i++) { |
| 67 | if (config->pcie_clk_config_flag[i] & PCIE_CLK_FREE_RUNNING) |
| 68 | m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING; |
| 69 | else if (config->pcie_clk_config_flag[i] & PCIE_CLK_LAN) |
| 70 | m_cfg->PcieClkSrcUsage[i] = FSP_CLK_LAN; |
| 71 | else |
| 72 | m_cfg->PcieClkSrcUsage[i] = FSP_CLK_NOTUSED; |
| 73 | m_cfg->PcieClkSrcClkReq[i] = FSP_CLK_NOTUSED; |
| 74 | } |
| 75 | |
| 76 | /* PCIE ports */ |
Subrata Banik | 3a183bc | 2023-06-20 20:29:29 +0530 | [diff] [blame] | 77 | if (CONFIG(SOC_INTEL_METEORLAKE_U_H)) { |
Subrata Banik | 53d7e70 | 2023-06-02 16:07:25 +0530 | [diff] [blame] | 78 | m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pcie_rp_table()); |
| 79 | m_cfg->PchPcieRpEnableMask = 0; /* Don't care about PCH PCIE RP Mask */ |
| 80 | pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, config->pcie_rp, |
| 81 | get_max_pcie_port()); |
| 82 | } else { |
| 83 | /* |
| 84 | * FIXME: Implement PCIe RP mask for `PchPcieRpEnableMask` and |
| 85 | * perform pcie_rp_init(). |
| 86 | */ |
| 87 | m_cfg->PcieRpEnableMask = 0; /* Don't care about SOC/IOE PCIE RP Mask */ |
| 88 | } |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 89 | } |
| 90 | |
| 91 | static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg, |
| 92 | const struct soc_intel_meteorlake_config *config) |
| 93 | { |
| 94 | unsigned int i; |
| 95 | const struct ddi_port_upds { |
| 96 | uint8_t *ddc; |
| 97 | uint8_t *hpd; |
| 98 | } ddi_port_upds[] = { |
| 99 | [DDI_PORT_A] = {&m_cfg->DdiPortADdc, &m_cfg->DdiPortAHpd}, |
| 100 | [DDI_PORT_B] = {&m_cfg->DdiPortBDdc, &m_cfg->DdiPortBHpd}, |
| 101 | [DDI_PORT_C] = {&m_cfg->DdiPortCDdc, &m_cfg->DdiPortCHpd}, |
| 102 | [DDI_PORT_1] = {&m_cfg->DdiPort1Ddc, &m_cfg->DdiPort1Hpd}, |
| 103 | [DDI_PORT_2] = {&m_cfg->DdiPort2Ddc, &m_cfg->DdiPort2Hpd}, |
| 104 | [DDI_PORT_3] = {&m_cfg->DdiPort3Ddc, &m_cfg->DdiPort3Hpd}, |
| 105 | [DDI_PORT_4] = {&m_cfg->DdiPort4Ddc, &m_cfg->DdiPort4Hpd}, |
| 106 | }; |
| 107 | m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(PCI_DEVFN_IGD); |
| 108 | if (m_cfg->InternalGfx) { |
| 109 | /* IGD is enabled, set IGD stolen size to 64MB. */ |
| 110 | m_cfg->IgdDvmt50PreAlloc = IGD_SM_64MB; |
| 111 | /* DP port config */ |
| 112 | m_cfg->DdiPortAConfig = config->ddi_port_A_config; |
| 113 | m_cfg->DdiPortBConfig = config->ddi_port_B_config; |
| 114 | for (i = 0; i < ARRAY_SIZE(ddi_port_upds); i++) { |
| 115 | *ddi_port_upds[i].ddc = !!(config->ddi_ports_config[i] & |
| 116 | DDI_ENABLE_DDC); |
| 117 | *ddi_port_upds[i].hpd = !!(config->ddi_ports_config[i] & |
| 118 | DDI_ENABLE_HPD); |
| 119 | } |
| 120 | } else { |
| 121 | /* IGD is disabled, skip IGD init in FSP. */ |
| 122 | m_cfg->IgdDvmt50PreAlloc = 0; |
| 123 | /* DP port config */ |
| 124 | m_cfg->DdiPortAConfig = 0; |
| 125 | m_cfg->DdiPortBConfig = 0; |
| 126 | for (i = 0; i < ARRAY_SIZE(ddi_port_upds); i++) { |
| 127 | *ddi_port_upds[i].ddc = 0; |
| 128 | *ddi_port_upds[i].hpd = 0; |
| 129 | } |
| 130 | } |
| 131 | } |
| 132 | |
| 133 | static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg, |
| 134 | const struct soc_intel_meteorlake_config *config) |
| 135 | { |
Bora Guvendik | 9f15dee | 2023-05-15 14:28:44 -0700 | [diff] [blame] | 136 | unsigned int i; |
| 137 | |
Subrata Banik | 289f9a5 | 2023-01-20 21:38:05 +0530 | [diff] [blame] | 138 | m_cfg->SaGv = config->sagv; |
Bora Guvendik | 9f15dee | 2023-05-15 14:28:44 -0700 | [diff] [blame] | 139 | |
Subrata Banik | a193308 | 2023-05-22 14:22:37 +0530 | [diff] [blame] | 140 | if (m_cfg->SaGv) { |
| 141 | /* |
| 142 | * Set SaGv work points after reviewing the power and performance impact |
| 143 | * with SaGv set to 1 (Enabled) and various work points between 0-3 being |
| 144 | * enabled. |
| 145 | */ |
| 146 | if (config->sagv_wp_bitmap) |
| 147 | m_cfg->SaGvWpMask = config->sagv_wp_bitmap; |
| 148 | else |
| 149 | m_cfg->SaGvWpMask = SAGV_POINTS_0_1_2_3; |
Bora Guvendik | 9f15dee | 2023-05-15 14:28:44 -0700 | [diff] [blame] | 150 | |
| 151 | for (i = 0; i < HOB_MAX_SAGV_POINTS; i++) { |
| 152 | m_cfg->SaGvFreq[i] = config->sagv_freq_mhz[i]; |
| 153 | m_cfg->SaGvGear[i] = config->sagv_gear[i]; |
| 154 | } |
Subrata Banik | a193308 | 2023-05-22 14:22:37 +0530 | [diff] [blame] | 155 | } |
| 156 | |
Subrata Banik | 289f9a5 | 2023-01-20 21:38:05 +0530 | [diff] [blame] | 157 | m_cfg->RMT = config->rmt; |
Subrata Banik | 8dd962b | 2023-02-03 13:06:51 +0530 | [diff] [blame] | 158 | /* Enable MRC Fast Boot */ |
| 159 | m_cfg->MrcFastBoot = 1; |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 160 | } |
| 161 | |
| 162 | static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg, |
| 163 | const struct soc_intel_meteorlake_config *config) |
| 164 | { |
| 165 | m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; |
| 166 | /* CpuRatio Settings */ |
| 167 | if (config->cpu_ratio_override) |
| 168 | m_cfg->CpuRatio = config->cpu_ratio_override; |
| 169 | else |
| 170 | /* Set CpuRatio to match existing MSR value */ |
| 171 | m_cfg->CpuRatio = (rdmsr(MSR_FLEX_RATIO).lo >> 8) & 0xff; |
| 172 | |
| 173 | m_cfg->PrmrrSize = get_valid_prmrr_size(); |
Eran Mitrani | 222903e | 2022-12-19 11:27:10 -0800 | [diff] [blame] | 174 | m_cfg->HyperThreading = get_uint_option("hyper_threading", CONFIG(FSP_HYPERTHREADING)); |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 175 | } |
| 176 | |
Pratikkumar Prajapati | 10bd2a2 | 2023-06-05 18:18:16 -0700 | [diff] [blame] | 177 | static void fill_tme_params(FSP_M_CONFIG *m_cfg) |
| 178 | { |
| 179 | m_cfg->TmeEnable = CONFIG(INTEL_TME) && is_tme_supported(); |
| 180 | if (!m_cfg->TmeEnable) |
| 181 | return; |
| 182 | m_cfg->GenerateNewTmeKey = CONFIG(TME_KEY_REGENERATION_ON_WARM_BOOT); |
| 183 | if (m_cfg->GenerateNewTmeKey) { |
| 184 | uint32_t ram_top = get_ramtop_addr(); |
| 185 | if (!ram_top) { |
| 186 | printk(BIOS_WARNING, "Invalid exclusion range start address. " |
| 187 | "Full memory encryption is enabled.\n"); |
| 188 | return; |
| 189 | } |
| 190 | m_cfg->TmeExcludeBase = (ram_top - 16*MiB); |
| 191 | m_cfg->TmeExcludeSize = 16*MiB; |
| 192 | } |
| 193 | } |
| 194 | |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 195 | static void fill_fspm_security_params(FSP_M_CONFIG *m_cfg, |
| 196 | const struct soc_intel_meteorlake_config *config) |
| 197 | { |
| 198 | /* Disable BIOS Guard */ |
| 199 | m_cfg->BiosGuard = 0; |
Pratikkumar Prajapati | 10bd2a2 | 2023-06-05 18:18:16 -0700 | [diff] [blame] | 200 | fill_tme_params(m_cfg); |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 201 | } |
| 202 | |
| 203 | static void fill_fspm_uart_params(FSP_M_CONFIG *m_cfg, |
| 204 | const struct soc_intel_meteorlake_config *config) |
| 205 | { |
| 206 | if (CONFIG(DRIVERS_UART_8250IO)) |
| 207 | m_cfg->PcdIsaSerialUartBase = ISA_SERIAL_BASE_ADDR_3F8; |
| 208 | m_cfg->SerialIoUartDebugMode = PchSerialIoSkipInit; |
| 209 | m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; |
| 210 | } |
| 211 | |
| 212 | static void fill_fspm_ipu_params(FSP_M_CONFIG *m_cfg, |
| 213 | const struct soc_intel_meteorlake_config *config) |
| 214 | { |
| 215 | /* Image clock: disable all clocks for bypassing FSP pin mux */ |
| 216 | memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn)); |
| 217 | /* IPU */ |
| 218 | m_cfg->SaIpuEnable = is_devfn_enabled(PCI_DEVFN_IPU); |
| 219 | } |
| 220 | |
| 221 | static void fill_fspm_smbus_params(FSP_M_CONFIG *m_cfg, |
| 222 | const struct soc_intel_meteorlake_config *config) |
| 223 | { |
| 224 | m_cfg->SmbusEnable = is_devfn_enabled(PCI_DEVFN_SMBUS); |
| 225 | } |
| 226 | |
Jay Patel | 310698c | 2023-06-01 14:01:43 -0700 | [diff] [blame^] | 227 | static void fill_fspm_vr_config_params(FSP_M_CONFIG *m_cfg, |
| 228 | const struct soc_intel_meteorlake_config *config) |
| 229 | { |
| 230 | /* FastVmode Settings for VR domains */ |
| 231 | for (size_t domain = 0; domain < NUM_VR_DOMAINS; domain++) { |
| 232 | m_cfg->CepEnable[domain] = config->cep_enable[domain]; |
| 233 | if (m_cfg->CepEnable[domain]) { |
| 234 | m_cfg->EnableFastVmode[domain] = config->enable_fast_vmode[domain]; |
| 235 | if (m_cfg->EnableFastVmode[domain]) |
| 236 | m_cfg->IccLimit[domain] = config->fast_vmode_i_trip[domain]; |
| 237 | } |
| 238 | } |
| 239 | } |
| 240 | |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 241 | static void fill_fspm_misc_params(FSP_M_CONFIG *m_cfg, |
| 242 | const struct soc_intel_meteorlake_config *config) |
| 243 | { |
| 244 | /* Disable Lock PCU Thermal Management registers */ |
| 245 | m_cfg->LockPTMregs = 0; |
| 246 | |
| 247 | /* Skip CPU replacement check */ |
| 248 | m_cfg->SkipCpuReplacementCheck = !config->cpu_replacement_check; |
| 249 | |
| 250 | /* Skip GPIO configuration from FSP */ |
| 251 | m_cfg->GpioOverride = 0x1; |
Wonkyu Kim | e5f6ff8 | 2022-10-13 13:34:27 -0700 | [diff] [blame] | 252 | |
| 253 | /* Skip MBP HOB */ |
Kapil Porwal | e988cc2 | 2023-01-16 16:41:49 +0000 | [diff] [blame] | 254 | m_cfg->SkipMbpHob = !CONFIG(FSP_PUBLISH_MBP_HOB); |
Subrata Banik | f57eb1a | 2023-02-10 21:04:30 +0530 | [diff] [blame] | 255 | |
| 256 | m_cfg->SkipExtGfxScan = config->skip_ext_gfx_scan; |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 257 | } |
| 258 | |
| 259 | static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg, |
| 260 | const struct soc_intel_meteorlake_config *config) |
| 261 | { |
| 262 | /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ |
| 263 | m_cfg->PchHdaEnable = is_devfn_enabled(PCI_DEVFN_HDA); |
| 264 | m_cfg->PchHdaDspEnable = config->pch_hda_dsp_enable; |
| 265 | m_cfg->PchHdaIDispLinkTmode = config->pch_hda_idisp_link_tmode; |
| 266 | m_cfg->PchHdaIDispLinkFrequency = config->pch_hda_idisp_link_frequency; |
| 267 | m_cfg->PchHdaIDispCodecDisconnect = !config->pch_hda_idisp_codec_enable; |
Ronak Kanabar | b807a1d | 2023-05-31 10:28:51 +0530 | [diff] [blame] | 268 | |
| 269 | for (int i = 0; i < MAX_HD_AUDIO_SDI_LINKS; i++) |
| 270 | m_cfg->PchHdaSdiEnable[i] = config->pch_hda_sdi_enable[i]; |
| 271 | |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 272 | /* |
| 273 | * All the PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs are used by FSP only to |
| 274 | * configure GPIO pads for audio. Mainboard is expected to perform all GPIO |
| 275 | * configuration in coreboot and hence these UPDs are set to 0 to skip FSP GPIO |
| 276 | * configuration for audio pads. |
| 277 | */ |
| 278 | m_cfg->PchHdaAudioLinkHdaEnable = 0; |
| 279 | memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable)); |
| 280 | memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable)); |
| 281 | memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); |
| 282 | } |
| 283 | |
zhaojohn | a923a43 | 2022-09-22 20:33:57 -0700 | [diff] [blame] | 284 | static void fill_fspm_cnvi_params(FSP_M_CONFIG *m_cfg, |
| 285 | const struct soc_intel_meteorlake_config *config) |
| 286 | { |
| 287 | /* CNVi DDR RFI Mitigation */ |
| 288 | const struct device_path path[] = { |
| 289 | { .type = DEVICE_PATH_PCI, .pci.devfn = PCI_DEVFN_CNVI_WIFI }, |
| 290 | { .type = DEVICE_PATH_GENERIC, .generic.id = 0 } }; |
| 291 | const struct device *dev = find_dev_nested_path(pci_root_bus(), path, |
| 292 | ARRAY_SIZE(path)); |
| 293 | if (is_dev_enabled(dev)) |
| 294 | m_cfg->CnviDdrRfim = wifi_generic_cnvi_ddr_rfim_enabled(dev); |
| 295 | } |
| 296 | |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 297 | static void fill_fspm_ish_params(FSP_M_CONFIG *m_cfg, |
| 298 | const struct soc_intel_meteorlake_config *config) |
| 299 | { |
| 300 | m_cfg->PchIshEnable = is_devfn_enabled(PCI_DEVFN_ISH); |
| 301 | } |
| 302 | |
| 303 | static void fill_fspm_tcss_params(FSP_M_CONFIG *m_cfg, |
| 304 | const struct soc_intel_meteorlake_config *config) |
| 305 | { |
| 306 | int i, max_port; |
| 307 | |
| 308 | /* Tcss USB */ |
| 309 | m_cfg->TcssXhciEn = is_devfn_enabled(PCI_DEVFN_TCSS_XHCI); |
| 310 | m_cfg->TcssXdciEn = is_devfn_enabled(PCI_DEVFN_TCSS_XDCI); |
| 311 | |
| 312 | /* TCSS DMA */ |
| 313 | m_cfg->TcssDma0En = is_devfn_enabled(PCI_DEVFN_TCSS_DMA0); |
Ivy Jian | 4257e8c | 2022-09-12 14:42:58 +0800 | [diff] [blame] | 314 | m_cfg->TcssDma1En = is_devfn_enabled(PCI_DEVFN_TCSS_DMA1); |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 315 | |
| 316 | /* Enable TCSS port */ |
| 317 | max_port = get_max_tcss_port(); |
| 318 | m_cfg->UsbTcPortEnPreMem = 0; |
| 319 | for (i = 0; i < max_port; i++) |
| 320 | if (config->tcss_ports[i].enable) |
| 321 | m_cfg->UsbTcPortEnPreMem |= BIT(i); |
| 322 | } |
| 323 | |
| 324 | static void fill_fspm_usb4_params(FSP_M_CONFIG *m_cfg, |
| 325 | const struct soc_intel_meteorlake_config *config) |
| 326 | { |
Sridhar Siricilla | cb4d464 | 2022-09-26 12:12:20 +0530 | [diff] [blame] | 327 | m_cfg->TcssItbtPcie0En = is_devfn_enabled(PCI_DEVFN_TBT0); |
| 328 | m_cfg->TcssItbtPcie1En = is_devfn_enabled(PCI_DEVFN_TBT1); |
| 329 | m_cfg->TcssItbtPcie2En = is_devfn_enabled(PCI_DEVFN_TBT2); |
| 330 | m_cfg->TcssItbtPcie3En = is_devfn_enabled(PCI_DEVFN_TBT3); |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 331 | } |
| 332 | |
| 333 | static void fill_fspm_vtd_params(FSP_M_CONFIG *m_cfg, |
| 334 | const struct soc_intel_meteorlake_config *config) |
| 335 | { |
| 336 | m_cfg->VtdDisable = 0; |
| 337 | m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; |
| 338 | m_cfg->VtdBaseAddress[1] = VTVC0_BASE_ADDRESS; |
| 339 | |
| 340 | /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ |
| 341 | m_cfg->VmxEnable = CONFIG(ENABLE_VMX); |
| 342 | } |
| 343 | |
| 344 | static void fill_fspm_trace_params(FSP_M_CONFIG *m_cfg, |
| 345 | const struct soc_intel_meteorlake_config *config) |
| 346 | { |
| 347 | /* Set debug probe type */ |
vjadeja-intel | 0ddeaed | 2022-11-03 14:48:46 +0530 | [diff] [blame] | 348 | m_cfg->PlatformDebugOption = CONFIG_SOC_INTEL_METEORLAKE_DEBUG_CONSENT; |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 349 | |
| 350 | /* CrashLog config */ |
| 351 | if (CONFIG(SOC_INTEL_CRASHLOG)) { |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 352 | m_cfg->CpuCrashLogEnable = 1; |
| 353 | } |
| 354 | } |
| 355 | |
| 356 | static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, |
| 357 | const struct soc_intel_meteorlake_config *config) |
| 358 | { |
Arthur Heymans | 4081d6c | 2022-07-29 10:45:52 +0200 | [diff] [blame] | 359 | void (*fill_fspm_params[])(FSP_M_CONFIG *m_cfg, |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 360 | const struct soc_intel_meteorlake_config *config) = { |
| 361 | fill_fspm_igd_params, |
| 362 | fill_fspm_mrc_params, |
| 363 | fill_fspm_cpu_params, |
| 364 | fill_fspm_security_params, |
| 365 | fill_fspm_uart_params, |
| 366 | fill_fspm_ipu_params, |
| 367 | fill_fspm_smbus_params, |
| 368 | fill_fspm_misc_params, |
| 369 | fill_fspm_audio_params, |
zhaojohn | a923a43 | 2022-09-22 20:33:57 -0700 | [diff] [blame] | 370 | fill_fspm_cnvi_params, |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 371 | fill_fspm_pcie_rp_params, |
| 372 | fill_fspm_ish_params, |
| 373 | fill_fspm_tcss_params, |
| 374 | fill_fspm_usb4_params, |
| 375 | fill_fspm_vtd_params, |
| 376 | fill_fspm_trace_params, |
Jay Patel | 310698c | 2023-06-01 14:01:43 -0700 | [diff] [blame^] | 377 | fill_fspm_vr_config_params, |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 378 | }; |
| 379 | |
| 380 | for (size_t i = 0; i < ARRAY_SIZE(fill_fspm_params); i++) |
| 381 | fill_fspm_params[i](m_cfg, config); |
| 382 | } |
| 383 | |
| 384 | void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |
| 385 | { |
| 386 | const struct soc_intel_meteorlake_config *config; |
| 387 | FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; |
Subrata Banik | e88bee7 | 2022-06-27 16:51:44 +0530 | [diff] [blame] | 388 | FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 389 | |
Subrata Banik | e88bee7 | 2022-06-27 16:51:44 +0530 | [diff] [blame] | 390 | if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER)) { |
| 391 | if (CONFIG(CONSOLE_SERIAL) && CONFIG(FSP_ENABLE_SERIAL_DEBUG)) { |
| 392 | enum fsp_log_level log_level = fsp_map_console_log_level(); |
| 393 | arch_upd->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *) |
| 394 | fsp_debug_event_handler); |
| 395 | /* Set Serial debug message level */ |
| 396 | m_cfg->PcdSerialDebugLevel = log_level; |
| 397 | /* Set MRC debug level */ |
| 398 | m_cfg->SerialDebugMrcLevel = log_level; |
| 399 | } else { |
| 400 | /* Disable Serial debug message */ |
| 401 | m_cfg->PcdSerialDebugLevel = 0; |
| 402 | /* Disable MRC debug message */ |
| 403 | m_cfg->SerialDebugMrcLevel = 0; |
| 404 | } |
| 405 | } |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 406 | config = config_of_soc(); |
| 407 | |
| 408 | soc_memory_init_params(m_cfg, config); |
| 409 | mainboard_memory_init_params(mupd); |
| 410 | } |
| 411 | |
| 412 | __weak void mainboard_memory_init_params(FSPM_UPD *memupd) |
| 413 | { |
| 414 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 415 | } |